參數(shù)資料
型號(hào): STE2001DIE2
廠商: 意法半導(dǎo)體
英文描述: 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
中文描述: 65 × 128單芯片LCD控制器/驅(qū)動(dòng)
文件頁(yè)數(shù): 11/36頁(yè)
文件大?。?/td> 326K
代理商: STE2001DIE2
11/36
STE2001
Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0
Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1
Instruction Set
Two different instructions formats are provided:
- With D/C set to LOW
commands are sent to the Control circuitry.
- With D/C set to HIGH
the Data RAM is addressed Instructions have the syntax summarized in Table.1.
Reset (RES)
At power-on, all internal registers and RAM content are not defined. A Reset pulse must be applied on RES pad
(active low) to initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with
the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode.
The Default configurations is:
- Horizontal addressing (V = 0)
- Normal instruction set (H = 0)
- Normal display (MX = MY = TRS =BRS = 0)
- MUX 65 mode (MUX = 0)
D00IN1148
R16
to
R23
R24
to
R31
R48
to
R55
R56
to
R63
Row 0
to
Row 7
Row 8
to
Row15
Row 16
to
Row 23
Row 24
to
Row 31
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
0
1
2
3
4
5
6
7
123 124 125
121 122
120
126 127
ROW DRIVER
MUX 33 PHYSICAL MEMORY ROW
R64
Row 32
D00IN1148
R16
to
R23
R24
to
R31
R48
to
R55
R56
to
R63
Row 0
to
Row 7
Row 8
to
Row15
Row 16
to
Row 23
Row 24
to
Row 31
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
0
1
2
3
4
5
6
7
123 124 125
121 122
120
126 127
ROW DRIVER
MUX 33 PHYSICAL MEMORY ROW
R64
Row 32
相關(guān)PDF資料
PDF描述
STE2004S M16C; M16C/60 Series; Microcontroller; Bit Size: 32/16-bit CISC; ROM: 320K; RAM: 31K; ROM Type: Mask ROM; CPU: M16C/60 core; Minimum Instruction Execution Time (ns): 41.7 (@24MHz); Operating Frequency / Supply Voltage: 24MHz/3.0 to 5.5V, 10MHz/2.7 to 5.5V; Operating Ambient Temperature (°C): -20 to 85, -40 to 85; Package Code: PLQP0128KB-A (128P6Q-A)
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