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參數(shù)資料
| 型號： | ST95010WB3TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
| 中文描述： | 4K/2K/1K串行SPI EEPROM，帶有正時鐘選通 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 110K |
| 代理商： | ST95010WB3TR |
Write Status Register (WRSR)
TheWRSRinstructionallowsthe usertoselect the
size of protectedmemory. The user may read the
blocks but will be unable to write within the pro-
tected blocks. The blocks and respective WRSR
control bits are shown in Table4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggeredby the rising edge of S.
Thisrising edge of S mustappearno laterthanthe
16th clock cycle of the WRSR instruction of the
StatusRegister content (it mustnot appeara 17th
clockpulse before the rising edge of S), otherwise
the internal writesequenceis not performed.
ReadOperation
ThechipisfirstselectedbyputtingSlow.Theserial
one byte read instructionis followedby a onebyte
address (A7-A0), each bit being latched-in during
the rising edge of the clock(C). Bit 3 (seeTable 3)
of the read instruction contains address bit A8
(mostsignificantaddressbit).Thenthedatastored
inthememoryattheselectedaddressis shiftedout
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock
pulses. The byte address is automatically incre-
mentedto the next higher address after each byte
of datais shiftedout. When the highestaddressis
reached,theaddresscounterrollsoverto0hallow-
ing the read cycle to be continuedindefinitely.The
read operation is terminated by deselecting the
chip.Thechipcanbe deselectedat anytime during
dataoutput. Any read attemptduring a writecycle
will be rejectedand willdeselectthe chip.
C
D
AI01440
S
Q
A7
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
A6 A5 A4 A3 A2 A1 A0
A8
20 21 22 23
7
6
5
4
3
2
0
1
HIGH IMPEDANCE
DATA OUT
INSTRUCTION
BYTE ADDRESS
0
Figure 6. Read OperationSequence
Status Register Bits
Protected Block
Array Address Protected
BP1
BP0
ST95040
ST95020
ST95010
0
0
none
none
none
none
0
1
Upper quarter
180h - 1FFh
C0h - FFh
60h - 7Fh
1
0
Upper half
100h - 1FFh
80h - FFh
40h - 7Fh
1
1
Whole memory
000h - 1FFh
00h - FFh
00h - 7Fh
Table4. WriteProtectedBlock Size
Notes:
A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8is only activeon ST95040.
6/18
ST95040, ST95020, ST95010
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| ST95020WB6TR | 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ST95010WB6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM |
| ST95010WB6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
| ST95010WM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM |
| ST95010WM1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
| ST95010WM3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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