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參數(shù)資料
| 型號(hào)： | ST95010WB3TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
| 中文描述： | 4K/2K/1K串行SPI EEPROM，帶有正時(shí)鐘選通 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 110K |
| 代理商： | ST95010WB3TR |
Hold (HOLD).
The HOLD pin is used to pause
serial communications with the Memory without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validatedby
a high tolowtransitionon HOLDwhenC islow. To
resumethecommunications,HOLDisbroughthigh
whileC is low.Duringthe Hold conditionD, Q,and
C are at a high impedancestate.
Whenthe Memoryis underthe Holdcondition,it is
possibletodeselectthedevice.However,theserial
communications will remain paused after a rese-
lect, and the chip will be reset.
TheMemorycan bedrivenbyamicrocontrollerwith
its SPI peripheral running in either of the two fol-
lowingmodes:(CPOL,CPHA) = (’0’, ’0’)or (CPOL,
CPHA) = (’1’, ’1’).
Forthesetwomodes,inputdatais latchedinby the
low to high transitionof clockC, andoutputdatais
available from the high to low transition of Clock
(C).
Thedifferencebetween(CPOL,CPHA)= (0,0)and
(CPOL,CPHA) = (1, 1) is the stand-bypolarity:C
remains at ’0’ for (CPOL, CPHA) = (0, 0) and C
remainsat ’1’for(CPOL,CPHA)=(1,1)whenthere
is no data transfer.
OPERATIONS
All instructions, addressesand data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
thechipselect(S) goeslow.Priortoanyoperation,
a one-byteinstructioncode must be enteredin the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C).Toenter an instructioncode, the productmust
have been previously selected (S = low). Table 3
shows the instruction set and format for device
operation. If an invalid instructionis sent (one not
contained in Table 3), the chip is automatically
deselected. For operationsthat read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address,otherwise,it is a don’tcare.
WriteEnable(WREN) and WriteDisable(WRDI)
The Memory contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation.The WREN instructionwill set the latch
and the WRDI instruction will reset the latch. The
latchis reset under the following conditions:
– W pin is low
– Poweron
– WRDIinstruction executed
– WRSRinstructionexecuted
– WRITEinstruction executed
As soon as the WREN or WRDI instruction is
received by the memory, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.
Read StatusRegister (RDSR)
TheRDSRinstructionprovidesaccesstothestatus
register. The status register may be read at any
time,evenduringa writeto thememoryoperation.
If a Read Statusregisterreaches the 8thbit of the
Status register, an additional 9th clock pulse will
wrap around to read the 1st bit of theStatus Reg-
ister
The status register format is as follows:
b7
b0
1
1
1
1
BP1
BP0
WEL
WIP
BP1, BP0: Read and write bits
WEL, WIP: Read only bits.
b7 to b4: Read only bits.
Instruction
Description
Instruction Format
WREN
Set Write Enable Latch
0000 0110
WRDI
Reset Write Enable Latch
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read Data from Memory Array
0000 A
8
011
WRITE
Write Data to Memory Array
0000 A
8
010
Notes:
A
8
= 1,Upper page selected on ST95040.
A
8
= 0,Lower page selected on ST95040.
Table3. InstructionSet
4/18
ST95040, ST95020, ST95010
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相關(guān)代理商/技術(shù)參數(shù) |
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| ST95010WB6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM |
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| ST95010WM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM |
| ST95010WM1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
| ST95010WM3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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