參數(shù)資料
型號: ST95010WB3TR
廠商: 意法半導體
元件分類: DRAM
英文描述: 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
中文描述: 4K/2K/1K串行SPI EEPROM,帶有正時鐘選通
文件頁數(shù): 5/18頁
文件大小: 110K
代理商: ST95010WB3TR
AI01272
HOLD
S
W
Control Logic
High
Voltage
Generator
I/O Shift Register
Address
Register
and Counter
Data
Register
16 Bytes
X Decoder
Y
Block
Protect
C
D
Q
Status
Figure 5. Block Diagram
During a write to the memory operation to the
memory array, all bits BP1, BP0, WEL, WIP are
valid and can be read. Duringa writeto the status
register, onlythe bitsWEL and WIP are valid and
can be read. The values of BP1 and BP0 read at
thattimecorrespondto thepreviouscontentsof the
statusregister.
TheWrite-In-Process(WIP)read-onlybit indicates
whethertheMemoryis busywith a writeoperation.
Whenset to a ’1’a writeis in progress,when set to
a ’0’no write is in progress.
The Write Enable Latch (WEL) read-only bit indi-
catesthe statusofthe writeenablelatch.When set
to a ’1’the latchis set, when setto a ’0’the latch is
reset. The Block Protect (BP0 and BP1) bits indi-
cate the extent of the protectionemployed. These
bitsare set by the userissuing the WRSR instruc-
tion. These bits are non-volatile.
5/18
ST95040, ST95020, ST95010
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