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參數(shù)資料
| 型號： | ST92T141K4M6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 25 MHz, MICROCONTROLLER, PDSO34 |
| 封裝： | PLASTIC, SO-34 |
| 文件頁數(shù)： | 63/179頁 |
| 文件大?。?/td> | 1905K |
| 代理商： | ST92T141K4M6 |
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ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
INTERRUPT CONTROL REGISTER (AD_ICR)
The Interrupt Control Register contains the three
priority level bits, the two source flags, and their bit
mask:
INTERRUPT CONTROL REGISTER (AD_ICR)
R254 - Read/Write
Register Page: 63
Reset Value: 0000 1111 (0Fh)
Bit 7 = ECV:
End of Conversion.
This bit is automatically set by hardware after a
group of conversions is completed. It must be re-
set by the user, before returning from the Interrupt
Service Routine. Setting this bit by software will
cause a software interrupt request to be generat-
ed.
0: No End of Conversion event occurred
1: An End of Conversion event occurred
Bit 6 = AWD:
Analog Watchdog.
This is automatically set by hardware whenever ei-
ther of the two monitored analog inputs goes out of
bounds. The threshold values are stored in regis-
ters F8h and FAh for channel 6, and in registers
F9h and FBh for channel 7 respectively. The Com-
pare Result Register (CRR) keeps track of the an-
alog inputs exceeding the thresholds.
The AWD bit must be reset by the user, before re-
turning from the Interrupt Service Routine. Setting
this bit by software will cause a software interrupt
request to be generated.
0: No Analog Watchdog event occurred
1: An Analog Watchdog event occurred
Bit 5 = ECI:
End of Conversion Interrupt Enable.
This bit masks the End of Conversion interrupt re-
quest.
0: Mask End of Conversion interrupts
1: Enable End of Conversion interrupts
Bit 4 = AWDI:
Analog Watchdog Interrupt Enable.
This bit masks or enables the Analog Watchdog
interrupt request.
0: Mask Analog Watchdog interrupts
1: Enable Analog Watchdog interrupts
Bit 3 = Reserved.
Bit 2:0 = PL[2:0]:
A/D Interrupt Priority Level.
These three bits allow selection of the Interrupt pri-
ority level for the ADC.
INTERRUPT VECTOR REGISTER (AD_IVR)
R255 - Read/Write
Register Page: 63
Reset Value: xxxx xx10 (x2h)
Bit 7:2 = V[7:2]:
A/D Interrupt Vector.
This vector should be programmed by the User to
point to the first memory location in the Interrupt
Vector table containing the starting addresses of
the A/D interrupt service routines.
Bit 1 = W1:
Word Select.
This bit is set and cleared by hardware, according
to the A/D interrupt source.
0: Interrupt source is the Analog Watchdog, point-
ing to the lower word of the A/D interrupt service
block (defined by V[7:2]).
1:Interrupt source is the End of Conversion inter-
rupt, thus pointing to the upper word.
Note: When two requests occur simultaneously,
the Analog Watchdog Request has priority over
the End of Conversion request, which is held
pending.
Bit 0 = Reserved. Forced by hardware to 0.
70
ECV
AWD
ECI
AWDI
X
PL2
PL1
PL0
70
V7
V6
V5
V4
V3
V2
W1
0
9
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