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參數(shù)資料
| 型號： | ST92T141K4M6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 25 MHz, MICROCONTROLLER, PDSO34 |
| 封裝： | PLASTIC, SO-34 |
| 文件頁數(shù)： | 52/179頁 |
| 文件大?。?/td> | 1905K |
| 代理商： | ST92T141K4M6 |
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.5.6 Register Description
DATA REGISTER (SPDR)
R240 - Read/Write
Register Page: 7
Reset Value: 0000 0000 (00h)
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data register, the buffer is ac-
tually being read.
Warning: A write to the DR register places data di-
rectly into the shift register for transmission.
A read to the DR register returns the value located
in the buffer and not the content of the shift regis-
ter (see Figure 73).
CONTROL REGISTER (SPCR)
R241 - Read/Write
Register Page: 7
Reset Value: 0000 0000 (00h)
Bit 7 = SPIE
Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever either
SPIF or MODF are set in the SR register while
the other flag is 0.
Bit 6 = SPOE
Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 7.5.4.5 Master Mode Fault).
0: SPI alternate functions disabled (MISO, MOSI
and SCK can only work as input)
1: SPI alternate functions enabled (MISO, MOSI
and SCK can work as input or output depending
on the value of MSTR)
Note: To use the MISO, MOSI and SCK alternate
functions (input or output), the corresponding I/O
port must be programmed as alternate function
output.
Bit 5 = SPIS
Interrupt Selection.
This bit is set and cleared by software.
0: Interrupt source is external interrupt
1: Interrupt source is SPI
Bit 4 = MSTR
Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 7.5.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
Bit 3 = CPOL
Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA
Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0]
Serial peripheral rate.
These bits are set and cleared by software. They
select one of four baud rates to be used as the se-
rial clock when the device is a master.
These 2 bits have no effect in slave mode.
Table 28. Serial Peripheral Baud Rate
70
D7
D6
D5
D4
D3
D2
D1
D0
70
SPIE
SPOE SPIS MSTR
CPOL
CPHA
SPR1
SPR0
INTCLK Clock Divide
SPR1
SPR0
20
0
40
1
16
1
0
32
1
9
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