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參數(shù)資料
| 型號(hào)： | ST72T774S9T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁(yè)數(shù)： | 85/144頁(yè) |
| 文件大?。?/td> | 1280K |
| 代理商： | ST72T774S9T1 |
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ST72774/ST727754/ST72734
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16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
In this section, the index,
i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free
running counter after a transition detected by the
ICAP
i pin (see figure 5).
IC
i Rregister is a read-only register.
The active transition is software programmable
through the IEDG
i bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (
fCPU/(CC1.CC0)).
Procedure
To use the input capture function select the
following in the CR2 register:
– Select the timer clock (CC1-CC0) (see Table 15
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When an input capture occurs:
– ICF
i bit is set.
– The IC
iR register contains the value of the free
running counter on the active transition on the
ICAP
i pin (see Figure 32).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request is
done by:
1. Reading the SR register while the ICF
i bit is set.
2. An access (read or write) to the IC
iLR register.
After reading the IC
iHR register, transfer of input
capture data is inhibited until the IC
iLR register is
also read.
The IC
iR register always contains the free running
counter value which corresponds to the most
recent input capture.
MS Byte
LS Byte
IC
iRICiHR
IC
iLR
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