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參數(shù)資料
| 型號(hào)： | ST72P63BH4T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, LQFP-48 |
| 文件頁(yè)數(shù)： | 84/145頁(yè) |
| 文件大?。?/td> | 2984K |
| 代理商： | ST72P63BH4T1 |
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
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Watchdog timer (Cont’d)
Table 16. Watchdog timing (fCPU = 8 MHz)
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
12.1.4 Software Watchdog option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
12.1.5 Hardware Watchdog option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
12.1.6 Low power modes
WAIT instruction
No effect on Watchdog.
HALT instruction
If the Watchdog reset on Halt option is selected by
option byte, a HALT instruction causes an immedi-
ate reset generation if the Watchdog is activated
(WDGA bit is set).
12.1.6.1 Using Halt mode with the WDG
(option)
If the Watchdog reset on Halt option is not select-
ed by option byte, the Halt mode can be used
when the watchdog is enabled.
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the WDG stops
counting and is no longer able to generate a reset
until the microcontroller receives an external inter-
rupt or a reset.
If an external interrupt is received, the WDG re-
starts counting after 4096 CPU clocks. If a reset is
generated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
12.1.7 Interrupts
None.
CR register
initial value
WDG timeout period
(ms)
Max
FFh
393.216
Min
C0h
6.144
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