參數(shù)資料
型號： ST72P63BH4T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件頁數(shù)： 83/145頁
文件大?。?/td> 2984K
代理商： ST72P63BH4T1
ST7263BDx ST7263BHx ST7263BKx ST7263BE
42/145
12 On-chip peripherals
12.1 Watchdog timer (WDG)
12.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
12.1.2 Main features
■
Programmable
free-running
counter
(64
increments of 49,152 CPU cycles)
■
Programmable reset
■
Reset (if watchdog activated) when the T6 bit
reaches zero
■
Optional
reset
on
HALT
instruction
(configurable by option byte)
■
Hardware Watchdog selectable by option byte.
12.1.3 Functional description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30s.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 16, ".
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Figure 26. Watchdog block diagram
RESET
WDGA
7-BIT DOWNCOUNTER
fCPU
T6
T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷49152
T1
T2
T3
T4
T5
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