參數(shù)資料
型號(hào)： ST72141K2B3/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 84/133頁(yè)
文件大?。?/td> 2615K
代理商： ST72141K2B3/XXX
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Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
54/133
MOTOR CONTROLLER (Cont’d)
At this time all registers with a preload function are
loaded (registers marked with (*) in Section 8.1.7).
The CI bit of MISR is set and if the CIM bit in the
MISR register is set an interrupt is generated.
An overflow of the MTIM timer generates an RPI
interrupt if the RIM bit is set.
The MTIM timer prescaler (Step ratio bits ST[3:0]
in the MPRSR register) is user programmable. Ac-
cess to this register is not allowed while the MTIM
timer is running (access is possible only before the
starting the timer by means of the MOE bit) but the
prescaler contents can be incremented/decre-
mented at the next commutation event by setting
the RMI (decrement) or RPI (increment) bits in the
MISR register. When this method is used, at the
next commutation event the prescaler value will be
updated but also all the MTIM timer-related regis-
ters will be shifted in the appropriate direction to
keep their value. After it has been taken into ac-
count, (at commutation) the RPI or RMI bit is reset.
Only one update per step is allowed, so if both RPI
and RMI are set together, RPI is taken into ac-
count at the next commutation and RMI is used
one commutation latter.
In switched mode, BEMF and demagnetization de-
tection are already possible in order to pass in au-
toswitched mode as soon as possible but Z and D
events do not affect the timer contents.
Warning: In this mode, MCOMP must never be
written to 0.
Table 18. Step Ratio Update
MOE bit SWA bit Clock State
Read
Ratio Increment
(Slow Down)
Ratio Decrement
(Speed-Up)
0
x
Disabled
Always
possible
Write the ST[3:0] value directly in the MPRSR register
1
0
Enabled
Set RPI bit in the MISR register
till next commutation
Set RMI bit in the MISR register
till next commutation
1
Enabled
Automatically updated according to MZREG value
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參數(shù)描述
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