參數(shù)資料
型號: ST72141K2B3/XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, PLASTIC, SDIP-32
文件頁數(shù): 45/133頁
文件大小: 2615K
代理商: ST72141K2B3/XXX
Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
19/133
3.2 RESET MANAGER
The RESET block includes three RESET sources
as shown in Figure 11:
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
A 4096 CPU clock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. Reset Block Diagram
fCPU
COU
N
T
E
R
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
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