參數(shù)資料
型號(hào)： ST72141K2B3/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 100/133頁(yè)
文件大?。?/td> 2615K
代理商： ST72141K2B3/XXX
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Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
69/133
MOTOR CONTROLLER (Cont’d)
Table 28. Step Ratio Update
CONTROL REGISTER A (MCRA)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = MOE: Output Enable bit.
0: Outputs and Clocks disabled
1: Outputs and Clocks enabled
Bit 6 = RST: Reset MTC registers.
Software can set this bit to reset all MTC registers
without resetting the ST7.
0: No MTC register reset
1: Reset all MTC registers
Bit 5 = SR: Sensor ON/OFF.
0: Sensorless mode
1: Sensor mode
Table 29. Sensor Mode Selection
Bit 4 = DAC: Direct Access to phase state register.
0: No Direct Access (reset value). In this mode all
the registers with a preload register are taken
into account at the C event.
1: Direct Access enabled. In this mode, write a val-
ue in the MPHST register to access the outputs
directly. All other registers with a preload regis-
ter are taken into account at the same time.
Table 30. DAC Bit Meaning
Note 1: When the MTC clock is disabled, the
MTIM counter is not reset but as in this case it is in
write access, a reset can be done by software.
Note 2: In direct access mode, only logical levels
(0 or 1) can be output on the MCOx pins. There is
no PWM signal generation in this mode.
Bit 3 = V0C1: Voltage/Current Mode
0: Voltage Mode
1: Current Mode
Bit 2 = SWA: Switched/Autoswitched Mode
0: Switched Mode
1: Autoswitched Mode
Table 31. Switched and Autoswitched Modes
Bit 1 = CFF: Current Feedback Filter
0: Current Feedback Filter disabled
1: Current Feedback Filter enabled
Bit 0 = DCB: Data Capture bit
0: Use MZPRV (ZN-1) for multiplication
1: Use MZREG (ZN) for multiplication
MOE
bit
SWA
bit
Clock
State
Read
Ratio
Increment
(Slow Down)
Ratio
Decrement
(Speed-Up)
0x
Disa-
bled
Al-
ways
possi-
ble
Write the ST[3:0] value di-
rectly in the MPRSR register
10
Ena-
bled
Set RPI bit in
the MISR reg-
ister till next
commutation
Set RMI bit in
the MISR reg-
ister till next
commutation
11
Ena-
bled
Updated automatically ac-
cording to MZREG value
70
MOE
RST
SR
DAC
V0C1
SWA
CFF
DCB
MOE bit
MCO[5:0] Output pin
State
0Tristate
1
Output enabled
SR
bit
Mode
OS2 bit
enable
Behaviour of the output
PWM
0
Sensors not
used
OS2
enabled
“Before D” behaviour & “af-
ter D” behaviour
1
Sensors
used
OS2
disabled
Only “after D” behaviour
MOE
bit
DAC
bit
Effect on Output
Effect on MTIM
Timer
0
x
High Z
Clock disabled
10
Standard
running mode
Standard running
mode
11
MPHST register value
(depending on MPOL
register value)
Clock disabled
SWA
bit
Commutation Type
MCOMP Register
access
0
Switched mode
Read/Write
1
Autoswitched mode
Read only
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