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| 型號： | ST5x86 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 100 and 120 MHz 3.45 Volt 5x86 CPU(微處理器) |
| 中文描述： | 100和120兆赫3.45伏特5x86的CPU（微處理器） |
| 文件頁數(shù)： | 6/39頁 |
| 文件大小： | 326K |
| 代理商： | ST5X86 |
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ST5x86
6/39
Figure 1.2. Performance Control Register 0 (PCR0)
Table 1.2. PCR0 Bit Definitions
BIT
POSITION
NAME
DESCRIPTION
0
RSTK_EN
Return Stack Enable.
If = 1: the Return Stack is enabled and RET instructions will speculatively execute the
code following the associated CALL to improve performance.
If = 0: the Return Stack is not enabled and optimum performance will not be achieved.
1
BTB_EN
Branch Target Buffer enable.
If = 1: the Branch Target Buffer is enabled and branch prediction occurs.
If = 0: no branch prediction will occur.
2
LOOP_EN
Loop Enable.
If = 1: the CPU will not flush the prefetch buffer if the destination of a jump is already
present in the prefetch buffer. This eliminates the need for a read from the cache and
thus improves performance.
3-6
Reserved.
7
LSSER
Load Store Serialize Enable (Reorder Disable).
If = 1: all memory reads and writes will occur in execution order (load store serializing
enabled, reordering disabled).
If = 0: memory reads and writes can be reordered for optimum performance (load store
serializing disabled, reordering enabled). Memory accesses in the address range 640K
to 1M will always be issued in execution order.
LSSER should be set to ensure that memory-mapped I/O devices operating outside of
the address range 640K to 1M will operate correctly.
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