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參數(shù)資料
| 型號： | ST5x86 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 100 and 120 MHz 3.45 Volt 5x86 CPU(微處理器) |
| 中文描述： | 100和120兆赫3.45伏特5x86的CPU（微處理器） |
| 文件頁數(shù)： | 15/39頁 |
| 文件大?。?/td> | 326K |
| 代理商： | ST5X86 |
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ST5x86
15/39
2.0 ELECTRICAL SPECIFICATIONS
This section providesinformation on electrical con-
nections,
absolute
maximum
mended
operating
conditions,
characteristics, and AC characteristics.
age values in Electrical Specifications are with
respect to V
SS
unless otherwise noted.
2.1 Electrical Connections
2.1.1 Power and Ground
Connections
and Decoupling
Testing and operating the 5x86 CPU requires the
use of standard high frequency techniques to
reduce parasitic effects. These effects can be min-
imized by filtering the DC power leads with
low-inductance decoupling capacitors, using low
impedance wiring, and by utilizing all of the V
CC
and GND pins.
2.2 Pull-Up/Pull-Down Resistors
Table 2.1. liststhe input pins that are internally con-
nected to pull-up and pull-down resistors. When
unused, these inputs do not require connection to
external
pull-up
or
pull-down
SUSP# pin is unique in that it is connected to a
pull-up resistor only when SUSP# is not asserted.
CLKMUL should not be connected to a switching
signal.
ratings,
recom-
and
DC
All volt-
resistors. The
Table 2.1. Pins Connected to Internal Pull-Up
and Pull-Down Resistors
It is recommended that the ADS#, LOCK# and
SMI# output pins be connected to pull-up resis-
tors, as indicated in Table 2.2. The external pull-ups
guarantee that the signals remain high (inactive)
during hold acknowledge states.
Table 2.2. Pins Requiring External Pull-Up
Resistors
SIGNAL
RESISTOR
A20M#
AHOLD
BOFF#
BS16#
BS8#
BRDY#
CLKMUL
EADS#
FLUSH#
IGNNE#
INVAL
KEN#
RDY#
SUSP#
UP#
WM_RST
20-k
pull-up
20-k
pull-down
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-up
20-k
pull-down
SIGNAL
EXTERNAL RESISTOR
ADS#
LOCK#
SMI#
20-k
pull-up
20-k
pull-up
20-k
pull-up
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