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參數(shù)資料
| 型號： | ST40RA200XH6E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372 |
| 文件頁數(shù)： | 7/94頁 |
| 文件大?。?/td> | 2144K |
| 代理商： | ST40RA200XH6E |
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B Implementation restrictions
ST40RA
15/92
B
Implementation restrictions
B.1
ST40 CPU
B.1.1
tas.b
The atomicity of the tas.b instruction is only guaranteed for processes executing on the ST40 CPU
core and should not be used to implement intermodule or interchip semaphores. Either use the
mailbox functionality or an appropriate software algorithm for such semaphores.
B.1.2
Store queue power-down
The store queue is considered part of the general CPU and independent power-down of this block
is not implemented.
B.1.3
UBC power-down
The UBC is considered part of the general CPU and independent power-down of this block is not
implemented.
B.1.4
System standby
To enter and leave standby it is necessary for the CPU to power down the system including memory
devices and then to enter standby by executing a sleep instruction. On leaving sleep and standby, it
may be necessary for the CPU to power itself up and subsequently power up the system and its
memory devices.
During the power-down and power-up sequences the main memory devices are not available. The
CPU therefore preloads the appropriate code into the cache as part of the power sequencing.
B.2
PCI
B.2.1
Clocking
PCI internal clock loop back is not implemented. To use the internal PCI clock, the pads
PCICLOCKOUT and PCICLOCKIN are connected to rollback the clock generator. Alternatively an
external clock source may be used.
B.2.2
Type 2 configuration accesses
Configuration space accesses to devices across a PCI bridge are implemented as type 2
operations on the PCI bus. In this implementation such accesses must be broken into a sequence of
byte operations. For example, access to a 32-bit register is through four single byte operations.
B.2.3
Software visible changes between STB1HC7 and ST40RAH8D
PCI PLL reprogramming required for H7 parts is no longer required for H8.
The PCI PLL register is renamed from PLLPCICR to CLKGENA.PLL2CR.
The register implementation for PCI MBAR mappings has changed between the STB1HC7 and
ST40RAH8D implementations and software device drivers should reflect this.
B.2.4
Error behavior
The implementation of local (PCI register) error handling is not fully implemented.
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