FIGURE 20. TRANSMIT R
參數(shù)資料
型號(hào): ST16C2552CJ44-F
廠商: Exar Corporation
文件頁數(shù): 26/34頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 3.3 V ~ 5 V
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1257-5
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
Data in
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
TX FIFO
Empty
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
ST16C2552
32
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2.2
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