參數(shù)資料
型號(hào)： SSTUG32865ET/S
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 鎖存器
英文描述： SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160
封裝： 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160
文件頁(yè)數(shù)： 28/28頁(yè)
文件大?。?/td> 154K
代理商： SSTUG32865ET/S
SSTUG32865_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 August 2007
9 of 28
NXP Semiconductors
SSTUG32865
1.8 V DDR2-1G registered buffer with parity
[1]
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
[2]
PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
[3]
This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched
LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ‘don’t care’ for PTYERR.
[4]
PTYERR0 is the previous state of output PTYERR.
7.2 Functional information
This 28-bit 1 : 2 registered buffer with parity is designed for 1.7 V to 2.0 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUG32865 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
A programming pin, SELDR, allows the user to select between two drive strength options
by tying this pin either LOW or HIGH on the DIMM. The truth table for these options is
shown in Table 6.
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (oating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS
RESET input must always be held at a valid logic HIGH or LOW level.
To ensure dened outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specied to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUG32865 ensures that the outputs remain LOW, thus
ensuring no glitches on the output.
The device monitors DCS0, DCS1, DCS2 and DCS3 inputs and will gate the Qn outputs
from changing states when all DCSn inputs are HIGH. If DCSn input is LOW, the Qn
outputs will function normally. The RESET input has priority over the DCSn control and
will force the Qn outputs LOW and the PTYERR output HIGH. If the DCSn-control
Table 6.
Truth table SELDR
Input
Mode
SELDR
L
high output drive
H
normal output drive
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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SSTUG32866EC/G 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G,518 功能描述:寄存器 1.8V REG RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTUG32866EC/G-T 功能描述:寄存器 1.8V REG BUF/PARITY-DDR2-1G RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTUG32866EC/S 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
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