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參數(shù)資料
| 型號(hào)： | SSTUA32864 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:1.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO) |
| 中文描述： | 1.8伏配置的注冊(cè)緩沖的DDR2 - 667 RDIMM特別應(yīng)用 |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | SSTUA32864 |
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9397 750 14757
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 May 2005
10 of 19
Philips Semiconductors
SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of t
ACT(max)
after RESET is taken HIGH.
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
INACT(max)
after RESET is taken LOW.
[3]
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 7:
Recommended operating conditions; T
amb
= 0
°
C to +70
°
C; V
DD
= 1.8 V
±
0.1 V; unless otherwise specified.
See
Figure 6
through
Figure 11
.
Symbol
Parameter
Conditions
f
clock
clock frequency
t
W
pulse duration, CK, CK HIGH or
LOW
t
ACT
differential inputs active time
t
INACT
differential inputs inactive time
t
su
setup time
DCS before CK
↑
, CK
↓
,
CSR HIGH
DCS before CK
↑
, CK
↓
,
CSR LOW
CSR, ODT, CKE, and data
before CK
↑
, CK
↓
t
h
hold time
DCS, CSR, ODT, CKE,
and data after CK
↑
, CK
↓
Timing requirements
Min
-
1
Typ
-
-
Max
450
-
Unit
MHz
ns
[1] [2]
-
-
-
-
10
15
-
ns
ns
ns
[1] [3]
-
0.7
0.5
-
-
ns
0.5
-
-
ns
0.5
-
-
ns
Table 8:
Recommended operating conditions; T
amb
= 0
°
C to +70
°
C; V
DD
= 1.8 V
±
0.1 V;
Class I, V
ref
= V
TT
= V
DD
×
0.5 and C
L
= 10 pF; unless otherwise specified. See
Figure 6
through
Figure 11
.
Symbol
Parameter
Conditions
f
MAX
maximum input clock frequency
t
PDM
propagation delay
CK and CK to output
t
PDMSS
propagation delay, simultaneous
switching
t
PHL
propagation delay
RESET to output
Switching characteristics
Min
450
Typ
-
-
-
Max
-
1.8
2.0
Unit
MHz
ns
ns
[1]
1.2
CK and CK to output
[1] [2]
-
-
-
3
ns
Table 9:
Recommended operating conditions; V
DD
= 1.8 V
±
0.1 V; unless otherwise specified.
Symbol
Parameter
dV/dt_r
rising edge slew rate
dV/dt_f
falling edge slew rate
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
Output edge rates
Conditions
Min
1
1
-
Typ
-
-
-
Max
4
4
1
Unit
V/ns
V/ns
V/ns
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