參數(shù)資料
型號(hào)： SSTU32865
廠商： NXP Semiconductors N.V.
英文描述： 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
中文描述： 1.8伏28位1:2登記緩沖區(qū)的DDR2 RDIMM特別平價(jià)
文件頁(yè)數(shù)： 6/29頁(yè)
文件大?。?/td> 157K
代理商： SSTU32865
9397 750 13799
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 28 September 2004
6 of 29
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
6.2 Pin description
Table 2:
Symbol
Ungated inputs
DCKE0, DCKE1
DODT0, DODT1
Chip Select gated inputs
D0 to D21
Pin description
Pin
Type
Description
U1, U2
T2, T1
SSTL_18
DRAM function pins not associated with Chip Select.
M1, B1, B2, C1, C2, D2, D1,
E1, E2, F2, M2, F1, G2, R1,
L2, H2, N2, N1, G1, P1, R2,
P2
SSTL_18
DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select inputs
DCS0, DCS1
J2, K2
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will
be LOW when a valid address/command is present. The
register can be programmed to re-drive all D-inputs only
(CSGATEEN = HIGH) when at least one Chip Select
input is LOW.
Re-driven outputs
Q0A to Q21A
V11, F12, G12, V6, V9, H12,
L12, V8, V12, N12, M12,
P12, V7, V10, T12, R12,
E12, A12, A10, A9, D12, A8
U11, F11, G11, U6, U9,
H11, L11, U8, U12, N11,
M11, P11, U7, U10, T11,
R11, E11, A11, B10, B9,
D11, B8
J12, K12, J11, K11
SSTL_18
Outputs of the register, valid after the specified clock
count and immediately following a rising edge of the
clock.
Q0B to Q21B
QCS0A, QDS1A,
QCS0B, QCS1B
QCKE0A, QCKE1A,
QCKE0B, QCKE1B
QODT0A, QODT1A,
QODT0B, QODT1B
Parity input
PARIN
A7, A6, B7, B6
B12, C12, B11, C11
A3
SSTL_18
Parity input for the D0 to D21 inputs. Arrives one clock
cycle after the corresponding data input.
Parity error
PTYERR
U4
open drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command
inputs. PTYERR will be active for two clock cycles, and
delayed by an additional clock cycle for compatibility with
final parity out timing on the industry-standard DDR2
register with parity (in JEDEC definition).
Program inputs
CSGATEEN
H1
1.8 V
LVCMOS
Chip Select Gate Enable. When HIGH, the D0 to D21
inputs will be latched only when at least one Chip Select
input is LOW during the rising edge of the clock. When
LOW, the D0 to D21 inputs will be latched and redriven
on every rising edge of the clock.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTU32865EG 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET 功能描述:寄存器 1.8V 28-BIT REG BUF/PARITY RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,518 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,551 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,557 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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