參數(shù)資料
型號： SSTU32865
廠商： NXP Semiconductors N.V.
英文描述： 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
中文描述： 1.8伏28位1:2登記緩沖區(qū)的DDR2 RDIMM特別平價
文件頁數(shù)： 17/29頁
文件大?。?/td> 157K
代理商： SSTU32865
9397 750 13799
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 28 September 2004
17 of 29
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of t
ACT(max)
after RESET is taken HIGH.
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
INACT(max)
after RESET is taken LOW.
[3]
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 9:
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
f
clock
clock frequency
t
W
pulse duration, CK, CK HIGH or
LOW
t
ACT
differential inputs active time
t
INACT
differential inputs inactive time
t
su
setup time, Chip Select
Timing requirements
Conditions
Min
-
1
Typ
-
-
Max
450
-
Unit
MHz
ns
[1] [2]
-
-
-
-
10
15
-
ns
ns
ns
[1] [3]
-
DCS0, DCS1 valid before
clock switching
Dn valid before clock
switching
PARIN before CK and CK
input to remain valid after
clock switching
PARIN after CK and CK
0.7
setup time, Data
0.5
-
-
ns
setup time, PARIN
hold time
0.5
0.5
-
-
-
-
ns
ns
t
h
hold time, PARIN
0.5
-
-
ns
Table 10:
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
f
MAX
maximum input clock frequency
t
PDM
propagation delay
t
LH
LOW-to-HIGH delay
t
HL
HIGH-to-LOW delay
t
PLH
LOW-to-HIGH propagation delay
t
PDMSS
propagation delay, simultaneous
switching
t
PHL
propagation delay
Switching characteristics
Conditions
Min
450
Typ
-
-
-
-
-
-
Max
-
1.8
3
3
3
2.0
Unit
MHz
ns
ns
ns
ns
ns
CK and CK to output
CK and CK to PTYERR
CK and CK to PTYERR
from RESET to PTYERR
CK and CK to output
[1]
1.41
1.2
1
-
[1] [2]
-
RESET to output
-
-
3
ns
Table 11:
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
dV/dt_r
rising edge slew rate
dV/dt_f
falling edge slew rate
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
Output edge rates
Conditions
Min
1
1
-
Typ
-
-
-
Max
4
4
1
Unit
V/ns
V/ns
V/ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTU32865EG 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET 功能描述:寄存器 1.8V 28-BIT REG BUF/PARITY RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,518 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,551 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,557 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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