參數(shù)資料
型號: SSTU32865
廠商: NXP Semiconductors N.V.
英文描述: 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
中文描述: 1.8伏28位1:2登記緩沖區(qū)的DDR2 RDIMM特別平價(jià)
文件頁數(shù): 27/29頁
文件大?。?/td> 157K
代理商: SSTU32865
9397 750 13799
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 28 September 2004
27 of 29
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
14. Revision history
Table 13:
Document ID
SSTU32865_2
Modifications:
Revision history
Release date
20040928
The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
Section 1 “General description”
: acronym TFBGA defined.
Section 2 “Features”
: acronym SSTL defined.
Additional features added to
Section 2 “Features”
Section 6 “Pinning information”
change ‘MCL to ‘m.c.l.’ and ‘MCH’ to ‘m.c.h.’
add descriptions for VDDL and VDDR in
Table 2 “Pin description”
added
Figure 2 “Pin configuration for TFBGA160”
added
Figure 3 “Ball mapping”
(replaces Table 2 “Ball mapping”)
Table 3 “Function table (each flip-flop)”
and
Table 4 “Parity and standby function table”
moved to
Section 7.1 on page 8
.
Table 3 “Function table (each flip-flop)”
: add
Table note 1
and its reference at ‘Outputs’.
Table 4 “Parity and standby function table”
:
Table note 2
: change ‘This transition assumes ...’ to ‘This condition assumes ...’.
Add
Table note 3
.
Section 7.3.4 “Power-up sequence”
: add ‘(HIGH)’ after ‘... and will be held clear’.
Table 6 “Limiting values”
:
Symbol V
i
changed to V
I
; Symbol V
o
changed to V
O
.
Symbols ESD
HBM
and ESD
MM
replaced with V
esd
(added model types under “Conditions”)
Table 7 “Recommended operating conditions”
:
change V
IH
(for data inputs) to V
IH(AC)
and V
IH(DC)
; condition changed to ‘data inputs (Dn)’
change V
IL
(for data inputs) to V
IL(AC)
and V
IL(DC)
; condition changed to ‘data inputs (Dn)
Table note split into 2 notes; references added.
Table 8 “Characteristics”
change I
DDD
Parameter from “dynamic operating current ...” to “dynamic operating current per
MHz ...”; change Unit from “
μ
A/MHz” to “
μ
A”.
change Typical value for I
DDD
(clock only) from TBD to 16
μ
A
change Typical value for I
DDD
(per each data input) from TBD to 19
μ
A
Table 9 “Timing requirements”
:
change symbol f
CLOCK
to f
clock
change f
clock
maximum value from 270 MHz to 450 MHz
change symbol t
SU
to t
su
; under ‘Conditions’, change ‘Chip Select’ to ‘DCS0, DCS1’.
change symbol t
H
to t
h
Table 10 “Switching characteristics”
:
change f
MAX
minimum value from 270 MHz to 450 MHz
change t
PDM
maximum value from 2.15 ns to 1.8 ns
change t
PDMSS
maximum value from 2.35 ns to 2.0 ns
Section 11.1 “Test circuit”
: acronym PRR defined; titles for
Figure 12
and
Figure 13
modified.
20040705
Product data
-
Data sheet status
Product data sheet
Change notice
-
Doc. number
9397 750 13799
Supersedes
SSTU32865-01
SSTU32865-01
9397 750 10942
-
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SSTU32865ET,518 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,551 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,557 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube