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參數(shù)資料
| 型號： | SST34HF1621-90-4E-LFP |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲器 |
| 英文描述： | 16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 8 X 10 MM, LFBGA-56 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 486K |
| 代理商： | SST34HF1621-90-4E-LFP |
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4
Data Sheet
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
2001 Silicon Storage Technology, Inc.
S71172-05-000
10/01 523
Toggle Bit (DQ
6
) is valid after the rising edge of sixth WE#
(or BEF#) pulse. See Figure 10 for Toggle Bit timing dia-
gram and Figure 22 for a flowchart.
Data Protection
The SST34HF1621/1641 provide both hardware
and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF1621/1641 provide a hardware block protec-
tion which protects the outermost 4 KWord in the larger
bank.The block is protected when WP# is held low. See
Figure 1 for Block-Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP
any in-progress operation will terminate and
return to Read mode (see Figure 18). When no internal
Program/Erase operation is in progress, a minimum period
of T
RHR
is required after RST# is driven high before a valid
Read can take place (see Figure 17).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.
Software Data Protection (SDP)
The SST34HF1621/1641 provide the JEDEC standard
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST34HF1621/1641 are shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to Read mode within T
RC.
The contents of DQ
15
-
DQ
8
are “Don’t Care” during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST34HF1621/1641 also contain the CFI information
to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write three-
byte sequence, same as Software ID Entry command with
98H (CFI Query command) to address 555H in the last byte
sequence. Once the device enters the CFI Query mode, the
system can read CFI data at the addresses given in Tables
5 through 7. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as
the SST34HF1621/1641 and manufacturer as SST. This
mode may be accessed by software operations only. The
hardware device ID Read operation, which is typically used
by programmers cannot be used on this device because of
the shared lines between flash and SRAM in the multi-chip
package. Therefore, application of high voltage to pin A
9
may damage this device. Users may use the software
Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Tables 3 and 4 for soft-
ware operation, Figure 14 for the software ID entry and
read timing diagram and Figure 23 for the ID entry com-
mand sequence flowchart.
TABLE
1: P
RODUCT
I
DENTIFICATION
ADDRESS
0000H
DATA
00BFH
Manufacturer’s ID
Device ID
SST34HF1621
SST34HF1641
0001H
0001H
2761H
2761H
T1.2 523
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| SST34HF1621A-70-4C-LFP | 功能描述:閃存 16M FLASH 2M SRAM RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST34HF1621A-70-4C-LFPE | 功能描述:閃存 16M FLASH 2M SRAM RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST34HF1621A-70-4E-LFP | 功能描述:閃存 16M FLASH 2M SRAM RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST34HF1621A-70-4E-LFPE | 功能描述:閃存 16M FLASH 2M SRAM RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST34HF1621C | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory |
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