參數(shù)資料
型號(hào): SST25VF010-20-4C-SAE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: PROM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 1M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 4.90 X 6 MM, LEAD FREE, MS-012AA, SOIC-8
文件頁(yè)數(shù): 10/22頁(yè)
文件大小: 283K
代理商: SST25VF010-20-4C-SAE
10
Data Sheet
1 Mbit SPI Serial Flash
SST25VF010
2003 Silicon Storage Technology, Inc.
S71233-01-000
8/03
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by address bits [A
23
-A
0
]. Address bits [A
MS
-A
12
]
(A
MS
= Most Significant address) are used to determine the
sector address (SA
X
), remaining address bits can be V
IL
or
V
IH.
CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status
register or wait T
SE
for the completion of the internal self-
timed Sector-Erase cycle. See Figure 7 for the Sector-
Erase sequence.
FIGURE 7: S
ECTOR
-E
RASE
S
EQUENCE
Block-Erase
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H, followed by
address bits [A
23
-A
0
]. Address bits [A
MS
-A
15
] (A
MS
= Most
significant address) are used to determine block address
(BA
X
), remaining address bits can be V
IL
or V
IH
. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
T
BE
for the completion of the internal self-timed Block-
Erase cycle. See Figure 8 for the Block-Erase sequence.
FIGURE 8: B
LOCK
-E
RASE
S
EQUENCE
CE#
SO
SI
SCK
ADD.
0 1 2 3 4 5 6
7 8
ADD.
ADD.
20
HIGH IMPEDANCE
15 16
23 24
31
MODE 0
MODE 3
1233 F07.1
MSB
MSB
CE#
SO
SI
SCK
ADD.
MSB
0 1 2 3 4 5 6
7 8
ADD.
ADD.
52
HIGH IMPEDANCE
15 16
23 24
31
MODE 0
MODE 3
1233 F08.1
MSB
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