參數(shù)資料
型號(hào)： SST25VF010-20-4C-SA
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類(lèi)： PROM
英文描述： 4 Mbit Uniform Sector, Serial Flash Memory
中文描述： 1M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 4.90 X 6 MM, MS-012AA, SOIC-8
文件頁(yè)數(shù)： 7/22頁(yè)
文件大小： 283K
代理商： SST25VF010-20-4C-SA
Data Sheet
1 Mbit SPI Serial Flash
SST25VF010
7
2003 Silicon Storage Technology, Inc.
S71233-01-000
8/03
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF010. The instruction bus cycles
are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
TABLE
6: D
EVICE
O
PERATION
I
NSTRUCTIONS
1
1. A
MS
= Most Significant Address
A
MS
= A
16
for SST25VF010
Address bits above the most significant bit of each density can be V
IL
or V
IH
2. One bus cycle is eight clock periods.
3. Operation: S
IN
= Serial In, S
OUT
= Serial Out
4. X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use A
MS
-A
12
, remaining addresses can be V
IL
or V
IH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
must be executed.
7. Block addresses for: use A
MS
-A
15
, remaining addresses can be V
IL
or V
IH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
11. Manufacturer’s ID is read with A
0
=0, and Device ID is read with A
0
=1. All other address bits are 00H. The Manufacturer’s and Device
ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 49H for SST25VF010
Bus Cycle
2
Cycle Type/Operation
3,4
Read
Sector-Erase
5,6
Block-Erase
5,7
Chip-Erase
6
Byte-Program
6
Auto Address Increment (AAI) Program
6,8
Read-Status-Register (RDSR)
Enable-Write-Status-Register (EWSR)
10
Write-Status-Register (WRSR)
10
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
1
2
3
4
5
S
IN
03H
20H
52H
60H
02H
AFH
05H
50H
01H
06H
04H
90H or
ABH
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
S
IN
S
OUT
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
D
OUT
-
Hi-Z
-
-
Hi-Z
S
IN
S
OUT
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
Note
9
-
-
-
-
Hi-Z
S
IN
A
7
-A
0
A
7
-A
0
A
7
-A
0
-
A
7
-A
0
A
7
-A
0
-
-
-.
-
-
ID Addr
11
S
OUT
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
Note
9
-
-
-
-
Hi-Z
S
IN
X
-
-
-
D
IN
D
IN
-
-
-
-
-
X
S
OUT
D
OUT
-
-
-
Hi-Z
Hi-Z
Note
9
-
-
-
-
D
OUT12
A
23
-A
16
A
23
-A
16
A
23
-A
16
-
A
23
-A
16
A
23
-A
16
X
-
Data
-
-
00H
A
15
-A
8
A
15
-A
8
A
15
-A
8
-
A
15
-A
8
A
15
-A
8
-
-
-
-
-
00H
T6.0 1233
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