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| 型號： | SPHE8200A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DVD SINGLE CHIP MPEG A/V PROCESSOR |
| 中文描述： | 影碟的單芯片MPEG A / V處理器 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 1816K |
| 代理商： | SPHE8200A |
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Sun usConidenia
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5.11. Video Post Processing
SEONLY
U
Interfa
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A
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r
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l
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m
i
i
n
n
a
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y
y
SPHE8200A
input
FIFO
Variable
length
decoder
Inverse
quantization
Inverse DCT
Motion
compensation
input
buffer
output
buffer
Picture
control
Decoding
control
display
information
Q matrix
DCT
buffer
Memory
Interface
Figure 5-8
: architecture of video decoding pipeline
5.10. Graphics Engine BondyPro
For thin-client or set-top box applications, 2D graphics capabilities
are key to system performance. This graphics engine is able to
perform fast BitBlt and 2D drawing functions. The graphics engine
is combined with 2 parts: graphics command interpreter and
graphics datapath. Upon receiving command from RISC,
interpreter will send micro-commands to graphics datapath, where
raster operations are executed.
RISC
subsyste
Grap
comma
interpret
Grap
data
Graph
work
Memo
Figure 5-9
: BondyPro architecture
SPHE8200 includes powerful video-post-processing facilities to
provide high video quality. It perform following functions:
YUV411, YUV420, YUV422 and 8-bit indexed color
SIF to CCIR601 interpolation
MPEG1 CIF filter
MPEG1/2 chroma vertical interpolation
Up to 1/2x horizontal decimation
Up to 1/512x vertical decimation
Up to 1024x horizontal expansion
Up to 1024x vertical expansion
Powerful de-interlacing hardware
Pan and scan function
De-flicker during interlaced display
Video contrast/bright/color enhancement
During runtime video post-processing hardware will fetch video
sources from framebuffer and process the data as in the following
figure.
input
buffer
de-interlac
line
buffer
from
memory
interface
Vertical
filtering
dhroma
resampl
to
display
interface
de-interlac
buffer
CIF and
horizonta
expansio
5.12. Audio DSP
The SPHE8200 contains a high-performance 24-bit audio DSP
optimized for embedded systems. The DSP processor can fetch
operands
from
memories
and
perform
multiplication-and-accumulation (MAC) in one cycle. During
execution the DSP fetches instruction from main-memory or IROM,
at the same time the ICACHE will store the LRU instructions.
Data are loaded from and to main-memory by using the
cycle-stealing DMA channels. There are 3 independent
cycle-stealing DMA channels that allow DSP run without stalled by
memory access.
The DSP works closely with RISC processors by using mailbox
registers or shared-memory protocol. When downloaded with
different codec firmware the DSP could support multi-standard
audio and act as an accelerator for RISC in some case.
DSP
ICACHE
IROM
data
ROM
data
RAM
data
ROM
data
RAM
BIU
Memory
interface
audio
interface
controller
Figure 5-10
: Audio DSP architecture
Sunplus Technology Co., Ltd.
Proprietary & Confidential
21
OCT. 07, 2003
Preliminary Version: 0.2
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