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| 型號： | SPHE8200A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DVD SINGLE CHIP MPEG A/V PROCESSOR |
| 中文描述： | 影碟的單芯片MPEG A / V處理器 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 1816K |
| 代理商： | SPHE8200A |
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SPHE8200A
5.5. ROM/Flash/SRAM controller
The SPHE8200 provides flexible connections to external ROM,
Flash or SRAM (RFS). It can support up to 4 external RFS devices
by using different chip-selects (R_CS_B[3:0]). The firmware can
configure RFS memory anchor registers and map these devices
into locations of memory space. For each memory space it can
be in flash mode or in ISA mode. In FLASH mode the access
timing is decided by wait-state setting, while in ISA mode the
controller will reference external IO_CHRDY input.
Processor
local bus
Prefetch
buffer
Address
sequencer
Address
translator
External
ROM
interface
Wait state
generation
Figure 5-4
: ROM/FLASH/SRAM controller
oe_setup
wait
ADDR[]
WEB
DATA[]
OEB
CSB
oe_hold
we_setup
we_hold
DATA (for write)
Address (read)
ROM/Flash mode
Data (read)
wait
Address (write)
data is sampled at this point
Figure 5-5
: ROM/FLASH/SRAM mode timing
oe_setup
wait
ADDR[]
WEB
IO_RDY
DATA[]
OEB
CSB
oe_hold
iochrdy_hold
we_setup
we_hold
DATA (for write)
Address (read)
ISA MODE
Data (read)
iochrdy_hold
wait
Address (write)
data is sampled at this point
Figure 5-6
: ISA mode timing
5.6. RISC Memory Interface
RISC memory interface provides a fast-path between processor
local bus and system memory bus. Local bus transactions are
mapped to system memory bus tasks.
5.7. Peripheral Control Interface
RISC firmware controls on-chip devices (such as video decoder,
audio decoder..) by a dedicated peripheral control interface.
Firmware controls the hardware behavior by writing to specific
hardware registers with this interface.
5.8. CSS/CPPM support
SPHE8200 have built-in CSS and CPPM hardware support. For
CSS the system supports accelerated DMA. For CPPM the
system supports C2_D/C2_E and C2_DCBC functions.
5.9. MPEG Video Decoder
The system incorporates a powerful MPEG video decoding
datapath and provides real-time video decoding of MPEGI/II
bitstream. The bitstream can come from Servo hardware, ATAPI,
TDM or UART. This enables various applications to be built over
SPHE8200 such as real-time broadcasting over Ethernet.
The video decoder is a hardwired MPEG1/2 datapath. The system
architecture is as in the figure. RISC subsystem is in charge of
de-multiplexing the data and buffering formatted video data into
video bitstream buffer resided in external SDRAM. Upon correct
timing video decoder will decode the bitstream and write back
reconstructed video frame for playback.
RISC
subsystem
Video
decoder
memory bus
a
External
SDRAM
b
b
r
r
control bus
Figure 5-7
: Interface between RISC and Video decoder
Advanced video decoding and display control mechanism is
included to prevent tearing effect.
Sunplus Technology Co., Ltd.
Proprietary & Confidential
20
OCT. 07, 2003
Preliminary Version: 0.2
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