參數(shù)資料
型號(hào)： SN74V3650-15PEU
廠商： Texas Instruments, Inc.
英文描述： 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
中文描述： 的3.3V的CMOS先入先出存儲(chǔ)器
文件頁(yè)數(shù)： 45/50頁(yè)
文件大?。?/td> 729K
代理商： SN74V3650-15PEU
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
depth-expansion configuration (FWFT mode only)
The SN74V3640 easily can be adapted to applications requiring depths greater than 1024 for the SN74V3640,
2048 for the SN74V3650, 4096 for the SN74V3660, 8192 for the SN74V3670, 16384 for the SN74V3680, and
32768 for the SN74V3690, with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the
data outputs of one FIFO connected to the data inputs of the next), with no external logic necessary. The
resulting configuration provides a total depth equivalent to the sum of the depths associated with each single
FIFO. Figure 24 shows a depth expansion using two SN74V3640, SN74V3650, SN74V3660, SN74V3670,
SN74V3680, and SN74V3690 devices.
Care should be taken to select FWFT mode during master reset for all FIFOs in the depth-expansion
configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)
until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK
of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device
’
s
OR line goes low, enabling a write to the next FIFO in line.
REN
Data In
Write Enable
Write Clock
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
FWFT/SI
Transfer Clock
WCLK
WEN
IR
Dn
RCLK
OR
REN
OE
Qn
WCLK
WEN
IR
Dn
RCLK
OR
OE
Qn
Read Clock
Read Enable
Input Ready
Output Ready
Output Enable
Data Out
GND
n
n
n
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
FWFT/SI
FWFT/SI
Figure 21. 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36, 65536
×
36
Depth-Expansion Block Diagram
For an empty-expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low
(i.e., valid data to appear on the last FIFO
’
s outputs) after a word has been written to the first FIFO is the sum
of the delays for each FIFO:
(n
–
1)
(4
transfer clock)
3t
RCLK
Where:
n
t
RCLK
= RCLK period
= number of FIFOs in the expansion
Note that extra cycles should be added for the possibility that the t
sk1
specification is not met between WCLK
and the transfer clock, or RCLK and the transfer clock, for the OR flag.
The ripple-down delay is noticeable only for the first word written to an empty-depth-expansion configuration.
There will be no delay evident for subsequent words written to the configuration.
The first free location created by reading from a full-depth-expansion configuration will bubble up from the last
FIFO to the previous one until, finally, it moves into the first FIFO of the chain. Each time a free location is created
in one FIFO of the chain, that FIFO
’
s IR line goes low, enabling the preceding FIFO to write a word to fill it.
P
(1)
相關(guān)PDF資料
PDF描述
SN74V3650-6PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3660-10PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3660-15PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3670-10PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3670-15PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74V3650-6PEU 功能描述:先進(jìn)先出 2048 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74V3650-7PEU 功能描述:先進(jìn)先出 2048 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74V3660-10PEU 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74V3660-15PEU 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74V3660-6PEU 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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