參數(shù)資料
型號(hào)： SN74BCT8374ANTE4
廠商： Texas Instruments, Inc.
英文描述： SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
中文描述： 掃描測(cè)試設(shè)備與八路D型邊沿觸發(fā)觸發(fā)器
文件頁數(shù)： 20/26頁
文件大小： 474K
代理商： SN74BCT8374ANTE4
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E – JUNE 1990 – REVISED JULY 1996
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
R1
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
R1
S1
7 V (tPZL, tPLZ, O.C.)
Open
(all others)
From Output
Under Test
Test
Point
R2
CL
(see Note A)
RL = R1 = R2
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
Data Input
1.5 V
1.5 V
3 V
3 V
0 V
0 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
tPHL
tPLH
tPLH
tPHL
Input
Out-of-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
tPHZ
tPLZ
0.3 V
tPZL
tPZH
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level enable)
Waveform 1
(see Note B)
Waveform 2
(see Note B)
0 V
VOH
VOL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, tr = tf
≤
2.5 ns, duty cycle = 50%.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 9. Load Circuits and Voltage Waveforms
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