參數(shù)資料
型號(hào)： SN74BCT8374ANTE4
廠商： Texas Instruments, Inc.
英文描述： SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
中文描述： 掃描測(cè)試設(shè)備與八路D型邊沿觸發(fā)觸發(fā)器
文件頁(yè)數(shù)： 12/26頁(yè)
文件大?。?/td> 474K
代理商： SN74BCT8374ANTE4
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E – JUNE 1990 – REVISED JULY 1996
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 1–0 as shown in Table 3. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 3. Boundary-Control Register Opcodes
BINARY CODE
BIT 1
→
BIT 0
MSB
→
LSB
00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
01
Pseudo-random pattern generation/16-bit mode (PRPG)
10
Parallel-signature analysis/16-bit mode (PSA)
11
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
It should be noted, in general, that while the control input BSCs (bits 17–16) are not included in the sample,
toggle, PSA, or PRPG algorithms, the output-enable BSC (bit 16 of the BSR) does control the drive state (active
or high impedance) of the device output terminals.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each
rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs
of the normal on-chip logic. Data in the shift register elements of the output BSCs is toggled on each rising edge
of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK
and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK.
This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip
logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are
generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value
of all zeroes will not produce additional patterns.
=
1D
1Q
2D
3D
4D
5D
6D
7D
8D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Figure 5. 16-Bit PRPG Configuration
相關(guān)PDF資料
PDF描述
SN54BCT8374AFK SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SN54BCT8374AJT SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SN74BCT8374ANT SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SN74BCT8374ADWR Replaced by BQ20Z80A-V110 : Impedance Track (TM) 1% accurate Gas Gauge for LiIon batteries SBS1.1 compliant 38-TSSOP -40 to 85
SN74BCT8374ADWRE4 Replaced by BQ20Z80A-V110 : Impedance Track (TM) 1% accurate Gas Gauge for LiIon batteries SBS1.1 compliant 38-TSSOP -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74BCT8374NT 制造商:Texas Instruments 功能描述:Flip Flop, Octal, D Type, 24 Pin, Plastic, DIP
SN74BCT899DW 制造商:Texas Instruments 功能描述:
SN74CB373384DBQR 制造商:Texas Instruments 功能描述:
SN74CB3Q16210DGGR 功能描述:數(shù)字總線開(kāi)關(guān) IC Fixed LDO Volt Reg RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
SN74CB3Q16210DGGRE4 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*