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| 型號： | SN74ABT2952APW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 中文描述： | 八路總線收發(fā)器和寄存器具有三態(tài)輸出 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 407K |
| 代理商： | SN74ABT2952APW |
SN54ABT2952A, SN74ABT2952A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS203D – AUGUST 1992 – REVISED JANUARY 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
Two 8-Bit Back-to-Back Registers Store
Data Flowing in Both Directions
Noninverting Outputs
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25
°
C
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
The ’ABT2952A transceivers consist of two 8-bit
back-to-back registers that store data flowing in
both directions between two bidirectional buses.
Data on the A or B bus is stored in the registers on
the low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB or CLKENBA) input is low. Taking the
output-enable (OEAB or OEBA) input low
accesses the data on either port.
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN54ABT2952A is characterized for
operation over the full military temperature range
of –55
°
C to 125
°
C. The SN74ABT2952A is
characterized for operation from –40
°
C to 85
°
C.
Copyright
1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
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13
B8
B7
B6
B5
B4
B3
B2
B1
OEAB
CLKAB
CLKENAB
GND
V
CC
A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
SN54ABT2952A . . . JT OR W PACKAGE
SN74ABT2952A . . . DB, DW, PW, OR NT PACKAGE
(TOP VIEW)
C
C
G
N
C
C
O
B
N
A
V
B
B
A
3 2 1 28 27
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A6
A5
A4
NC
A3
A2
A1
B5
B4
B3
NC
B2
B1
OEAB
4
26
SN54ABT2952A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
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PDF描述 |
|---|---|
| SN74ABT2952 | Octal Bus Transceivers And Registers With 3-State Outputs(八總線收發(fā)器和寄存器(三態(tài)輸出)) |
| SN74ABT32360 | 16 Bit Universal Tri-Port With Parity Generators/Checkers(16位TRI-PORT(三端口)帶奇偶發(fā)生器/校驗器) |
| SN74ABT3611PCB | 64 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY |
| SN74ABT3611PQ | 64 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY |
| SN74ABT3612PCB | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
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|---|---|
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