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參數(shù)資料
| 型號： | SN54BCT8374AJT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS |
| 中文描述： | 掃描測試設(shè)備與八路D型邊沿觸發(fā)觸發(fā)器 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 474K |
| 代理商： | SN54BCT8374AJT |
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E – JUNE 1990 – REVISED JULY 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device output terminals are placed in the high-impedance state,
the device input terminals remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output terminals. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output
terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and
is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured
in the input BSCs. The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
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