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參數(shù)資料
| 型號(hào)： | SK10E016PJ |
| 元件分類(lèi)： | 計(jì)數(shù)器 |
| 英文描述： | 10E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | SK10E016PJ |
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www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E016
Revision 1/August 22, 2001
Figure 3. 32-Bit Cascaded E016 Counter
P
rogrammable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider.
The TCLD pin (load on terminal count) when asserted
reloads the data present at the parallel input pin (Pn’s)
upon reaching terminal count (an all 1s state on the
outputs). Because this feedback is built internal to the
chip, the programmable division operation will run at very
nearly the same frequency as the maximum counting
frequency of the device. Figure 4 below illustrates the
input conditions necessary for utilizing the E016 as a
programmable divider set up to divide by 113.
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 – 113 = 8F16 = 1000 1111
where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure
4 will result in the waveforms of Figure 5. Note that
the TC* output is used as the divide output and the
pulse duration is equal to a full clock period. For
even divide ratios, twice the desired divide ratio can
be loaded into the E016, and the TC* output can
feed the clock input of a toggle flip-flop to create a
signal divided as desired with a 50% duty cycle.
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D
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t
a
R7
P6
P5
P4
P3
P2
P1
P0
P
2
HHHHHHH
L
3
HHHHHH
L
H
4
HHHHHH
L
5
HHHHH
L
H
l
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l
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2
1
H
LL
H
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3
1
H
L
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4
1
H
LLL
H
L
l
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l
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4
5
2
LLLLLL
H
L
5
2
LLLLLLL
H
6
5
2
LLLLLLLL
Preset Data Inputs
CE*
CLK
PE*
TC*
E016
LSB
CE*
CLK
PE*
TC*
E016
EL01
CE*
CLK
PE*
TC*
E016
CE*
CLK
PE*
TC*
E016
MSB
EL01
LOAD
CLOCK
Q0
Q7
P0
P7
Q0
Q7
P0
P7
Q0
Q7
P0
P7
Q0
Q7
P0
P7
PE*
CE*
TCLD
CLK
TC*
P7
P6
P5
P4
P3
P2
P1
P0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
H
L
H
L
HHHH
Application Information (continued)
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