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參數(shù)資料
| 型號： | SK10E016PJ |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | 10E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 142K |
| 代理商： | SK10E016PJ |
HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Revision 1/August 22, 2001
SK10/100E016
8-Bit Synchronous
Binary Up Counter
Description
Features
Functional Block Diagram
The SK10/100E016 is a high-speed synchronous,
presettable, cascadable 8-bit binary counter.
The counter features internal feedback of TC*, gated by
the TCLD (terminal count load) pin. When TCLD is LOW
(or left open, in which case it is pulled LOW by the internal
pull-downs), the TC* feedback is disabled, and counting
proceeds continuously, with TC* going LOW to indicate
an all-one state. When TCLD is HIGH, the TC* feedback
causes the counter to automatically reload upon TC* =
LOW, thus functioning as a programmable counter. The
Qn outputs do not need to be terminated for the count
function to operate properly.
To minimize noise and
power, unused Q outputs should be left unterminated.
700 MHz Minimum Count Frequency
1000 ps CLK to Q, TC*
Internal TC* Feedback (Gated)
8-Bit
Fully Synchronous Counting and TC* Generation
Asynchronous Master Reset
Internal 75 k
W Input Pulldown Resistors
Extended 100E VEE Range of –4.2V to –5.46V
Fully Compatible with MC10/100E016
Available in 28-Pin PLCC Package
ESD Protection of >4000V
CE*
Q0*
BIT 1
BIT 0
BIT 7
CE*
Q0*
Q1*
Q4*
Q5*
Q6*
Q2*
Q3*
P1
P7
Q0
Q1
Q7
5
TC*
PE
TCLD
CE*
PO
MR
CLK
MASTER
SLAVE
QOM*
QOM
BITS 2-6
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally without incurring a full gate delay.
8 Bit Binary Counter - Logic Counter
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