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參數(shù)資料
| 型號(hào)： | SK10E016PJ |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | 10E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | SK10E016PJ |
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www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E016
Revision 1/August 22, 2001
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Function Table
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very
wide bit width counters. The active low terminal count
(TC*) output and count enable input (CE*) greatly
facilitate the cascading of E016 devices. Two E016s
can be cascaded without the need for external gating;
however, for counters wider than 16 bits, external OR
gates are necessary for cascade implementations.
Figure 3 below illustrates the cascading of 4 E016s to
build a 32-bit high frequency counter. Note that the
E101 gates are used to OR the terminal count outputs
of the lower order E016s to control the counting
operation of the higher order bits. When the terminal
count of the preceding device (or devices) goes low
(the counter reaches an all 1s state), the more
significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition.
In addition, the preceding devices will also count one
bit, sending their terminal count outputs back to a high
state, disabling the count operation of the more
significant counters, and placing them back into hold
modes. Therefore, for an E016 in the chain to count,
all of the lower order terminal count outputs must
be in the low state. The bit width of the counter can
be increased or decreased by simply adding or
subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same
figure.
The maximum frequency of operation for the
cascaded counter chain is set by the propagation
delay of the TC* output, the necessary setup time
of the CE* input, and the propagation delay through
the OR gate controlling it (for 16-bit counters the
limitation is only the TC* propagation delay and the
CE* setup time). Figure 3 shows EL01 gates used
to control the count enable inputs; however, if the
frequency of operation is lower, a lower ECL OR gate
can be used. Using the worst case guarantees for
these parameters, the maximum count frequency
for a greater than 16-bit counter is 500 MHz, and
for a 16-bit counter is 625 MHz.
Note that this
assumes the trace delay between the TC* outputs
and the CE* inputs are negligible. If this is not the
case, estimates of these delays need to be added
to the calculations.
Application Information
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