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參數(shù)資料
| 型號： | SK100EL34WD |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 83K |
| 代理商： | SK100EL34WD |
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HIGH-PERFORMANCE PRODUCTS
SK100EL34W
Revision 3/June 26, 2002
AC Characteristics (continued)
CLK
Q0
Q1
Q2
EN*
Internal Clock
Disabled
Internal Clock
Enabled
The EN* signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its
assertion.
The internal dividers will maintain their state during the internal clock freeze and will return to
clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner, time, and relationship as they would have had the EN* signal not been asserted.
Timing Diagram
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| SK100EL39WDT | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| SK100EL52WU | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| SK100EL52WDT | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SK100EL56WDT | 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| SK100EL57WU | 100E SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, UUC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK100ELT21W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100EP111 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
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