參數(shù)資料
型號(hào)： SiI1161CT100
廠商： Silicon Image, Inc.
英文描述： PanelLink Receiver
中文描述： PanelLink接收機(jī)
文件頁(yè)數(shù)： 7/46頁(yè)
文件大?。?/td> 398K
代理商： SII1161CT100
SiI
1161
PanelLink Receiver
Data Sheet
3
SiI
-DS-0096-D
Electrical Specifications
Absolute Maximum Conditions
Symbol
V
CC
V
I
V
O
T
J
T
STG
Parameter
Min
-0.3
-0.3
-0.3
-65
Typ
Max
4.0
V
CC
+ 0.3
V
CC
+ 0.3
125
150
Units
V
V
V
°
C
°
C
Notes
1
2
Supply Voltage 3.3V
Input Voltage
Output Voltage
Junction Temperature
Storage Temperature
Notes
1. Permanent device damage may occur if absolute maximum conditions are exceeded.
2.
Functional operation should be restricted to the conditions described under Normal Operating
Conditions.
Normal Operating Conditions
Symbol
V
CC
V
CCN
AV
CCN
PV
CCN
T
A
θ
JCS
θ
JAS
θ
JCU
θ
JAU
Notes
1. Thermal resistance specified with package ePad soldered 100% to underlying PCB pad.
2. Thermal resistance specified with package ePad unsoldered to PCB.
Parameter
Min
3.0
0
Typ
3.3
25
13
26
19
58
Max
3.6
200
100
75
70
Units
V
mV
P-P
mV
P-P
mV
P-P
°
C
°
C/W
°
C/W
°
C/W
°
C/W
Notes
1
1
2
2
Supply Voltage
VCC, OVCC Supply Voltage Noise
AVCC Supply Voltage Noise
PVCC Supply Voltage Noise
Ambient Temperature (with power applied)
Thermal Resistance (Junction to Case) soldered
Thermal Resistance (Junction to Ambient) soldered
Thermal Resistance (Junction to Case) unsoldered
Thermal Resistance (Junction to Ambient) unsoldered
Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol
V
IH
V
IL
V
OH
V
OL
V
OL
(SDA)
Parameter
Conditions
Min
2
2.4
Typ
Max
0.8
0.4
0.4
Units
V
V
V
V
V
Notes
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
Low-level Output Voltage on
SDA
Input Clamp Voltage
Input Clamp Voltage
Output Clamp Voltage
Output Clamp Voltage
Output Leakage Current
I
OL
(SDA)=3mA
V
CINL
V
CIPL
V
CONL
V
COPL
I
OL
I
CL
= -18mA
I
CL
= 18mA
I
CL
= -18mA
I
CL
= 18mA
High Impedance
GND -0.8
IVCC + 0.8
GND -0.8
OVCC + 0.8
10
V
V
V
V
μ
A
1, 2
1, 2
1
1
-10
Note
1.
Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum
conditions for a pulse of greater than 3 ns or one third of the clock cycle.
2.
Applies to toggling inputs only. Strap selected options are fixed at power-up time.
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