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參數(shù)資料
| 型號： | SiI1161CT100 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PanelLink Receiver |
| 中文描述： | PanelLink接收機(jī) |
| 文件頁數(shù)： | 23/46頁 |
| 文件大小： | 398K |
| 代理商： | SII1161CT100 |
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SiI
1161
PanelLink Receiver
Data Sheet
19
SiI
-DS-0096-D
Pin Descriptions
Output Pins
Pin Name
QE23-
QE0
Pin #
See
SiI
1161
Pin
Diagram
Type
Out
Description
Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode
and to the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock
mode. During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pull-
down device brings the output to ground.
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
display time and a LOW level signifies blanking time. This output signal is synchronized with
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is
not
powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
QO23-
QO0
See
SiI
1161
Pin
Diagram
Out
ODCK
44
Out
DE
46
Out
HSYNC
VSYNC
CTL1
CTL2
CTL3
48
47
40
41
42
Out
Differential Signal Data Pins
Pin Name
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
Pin #
90
91
85
86
80
81
Type
Analog
Description
Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
RXC+
RXC-
EXT_RES
93
94
96
Analog
Analog Impedance Matching Control. An external 390
resistor must be connected between AVCC
and this pin.
Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
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| SiI1161CTU | PanelLink Receiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII1161CTU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1162 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
| SII1162CSU | 制造商:Silicon Image Inc 功能描述: |
| SII1169 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1171 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
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