參數(shù)資料
型號(hào)： SiI1161CT100
廠商： Silicon Image, Inc.
英文描述： PanelLink Receiver
中文描述： PanelLink接收機(jī)
文件頁(yè)數(shù)： 15/46頁(yè)
文件大?。?/td> 398K
代理商： SII1161CT100
SiI
1161
PanelLink Receiver
Data Sheet
11
SiI
-DS-0096-D
SiI
1161 (Programmable) Mode AC Specifications
SiI
1161 Mode AC timings are based on “Clock to Output” (CK2OUT) timing measurements. This methodology
provides a precise means of calculating setup and hold at any frequency and in any chip operating mode. C
L
indicates the load on the ODCK line. The load on the data/control line involved depends on CKST: for CKST=1,
the control/data pin load is C
L
; for CKST=0, the load is 2x C
L
.
Table 6.
SiI
1161 Mode AC Specifications
Program Option: ST=0 (Low Drive Strength)
Parameter
Conditions
ST
0
0
ST
0
0
0
0
ST
OCK_INV Setting
0
0
0
0
Limits (ns)
Data, HSYNC, VSYNC
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
ODCK, DE
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
Clock-to-Output Timing
CKST
X
X
CKST
1
0
1
0
CKST
C
L
5pF
5pF
C
L
5pF
10pF
5pF
10pF
C
L
Max
2.5
2.0
Max
2.5
1.5
2.7
1.7
Max
1X clock drive
2X clock drive
1X clock drive
2X clock drive
Min
0
0.4
0.4
1.2
0.8
1
0
1
T
CK2OUT
T
CK2OUT
1
0
1
0
5pF
10pF
5pF
10pF
0.0
-0.1
0.2
0.1
1.5
1.5
2.2
2.2
1.2
1.0
2.0
1.7
ODCK to Data
ODCK to DE,
HSYNC,
VSYNC
Program Option: ST=1 (High Drive Strength)
Parameter
Data, HSYNC, VSYNC
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
ODCK, DE
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
Clock-to-Output Timing
Conditions
ST
1
1
ST
1
1
1
1
ST
OCK_INV Setting
1
1
1
1
Limits (ns)
CKST
X
X
CKST
1
0
1
0
CKST
C
L
10pF
10pF
C
L
10pF
20pF
10pF
20pF
C
L
Max
2.5
2.0
Max
1.9
1.2
1.7
1.4
Max
2X clock drive
4X clock drive
2X clock drive
4X clock drive
Min
0
0.4
0.0
0.7
0.1
1
0
1
T
CK2OUT
T
CK2OUT
1
0
1
0
10pF
20pF
10pF
20pF
-0.2
-0.8
-0.3
-0.3
1.5
1.4
1.8
1.9
1.2
1.0
1.3
1.0
ODCK to Data
ODCK to DE,
HSYNC,
VSYNC
Notes
1. Output loading is equivalent to one (5pF), two (10pF) or four (20pF) CMOS input loads.
2. All transition time specifications at 70
°
C, minimum VCC.
3. Timing specifications in Table 6 apply to both one pixel per clock and two pixel per clock modes.
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