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參數(shù)資料
| 型號： | SII1161 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PanelLink Receiver |
| 中文描述： | PanelLink接收機 |
| 文件頁數(shù)： | 5/46頁 |
| 文件大小： | 398K |
| 代理商： | SII1161 |
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SiI
1161
PanelLink Receiver
Data Sheet
General Description
The
SiI
1161
technology to support high-resolution displays up to
UXGA (25-165MHz). This receiver supports up to true
color panels (24 bits per pixel, 16M colors) with both
one and two pixels per clock.
June 2005
SiI
-DS-0096-D
Features
receiver
uses
PanelLink
Digital
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the
same logical interface. System designers can be
assured that the interface will be stable through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a digital
interface solution that is quicker to market and lower in
cost.
Supports 10 meter cables at UXGA speed
I
2
C port for dynamic optimization of settings to
compensate for long cables and/or poor quality
transmitters
Flexible output drive controls to optimize timings
for all possible configurations
3.3V operation
Time staggered data output for reduced ground
bounce and lower EMI
Sync Detect feature for DVI “Hot Plugging”
ESD tolerant to 5kV (HBM) on all pins
Compliant with DVI 1.0
Guaranteed interoperability with DVI-compliant
transmitters
Low power standby mode; automatic entry into
standby mode with clock detect circuitry
Pb-free packaging (see page 41).
SiI
1161
Pin Diagram
OUTPUT
CLOCK
H
1
SiI
1161
100-Pin
TQFP
(Top View)
P
2
S
3
P
4
G
5
V
6
I
(
7
S
8
P
9
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
O
1
O
1
Q
2
Q
2
Q
2
Q
2
Q
2
Q
2
QE14
26
QE15
27
OGND
28
OVCC
29
QE16
30
QE17
31
QE18
32
QE19
33
QE20
34
QE21
35
QE22
36
QE23
37
VCC
38
GND
39
CTL1
40
CTL2
41
CTL3
42
OVCC
43
ODCK
44
OGND
45
DE
46
VSYNC
47
HSYNC
48
QO0
49
QO1
50
7
Q
7
Q
7
Q
7
Q
7
Q
7
Q
6
G
6
V
6
Q
6
Q
6
Q
6
Q
6
Q
6
Q
6
Q
6
Q
5
O
5
O
5
Q
5
Q
5
Q
5
Q
5
Q
5
Q
5
Q
SCL
(OCK_INV)
100
MODE
99
PGND
98
PVCC
97
EXT_RES
96
AVCC
95
RXC-
94
RXC+
93
AGND
92
RX0-
91
RX0+
90
AGND
89
AVCC
88
AGND
87
RX1-
86
RX1+
85
AVCC
84
AGND
83
AVCC
82
RX2-
81
RX2+
80
AGND
79
OVCC
78
QO23
77
OGND
76
D
S
ODD 8-bits RED
E
ODD 8-bits GREEN
EVEN 8-bits GREEN
ODD 8-bits BLUE
EVEN 8-bits BLUE
CONFIG. PINS
P
PWR
MGMT
G
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SiI1161CT100 | PanelLink Receiver |
| SiI1161CTU | PanelLink Receiver |
| SII1162 | PanelLink Transmitter |
| SII1169 | PanelLink Receiver |
| SII1171 | PanelLink Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII1161CT100 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1161CTU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1162 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
| SII1162CSU | 制造商:Silicon Image Inc 功能描述: |
| SII1169 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
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