- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365565 > SII1161 (Silicon Image, Inc.) PanelLink Receiver PDF資料下載
參數(shù)資料
| 型號： | SII1161 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PanelLink Receiver |
| 中文描述： | PanelLink接收機 |
| 文件頁數(shù)： | 26/46頁 |
| 文件大?。?/td> | 398K |
| 代理商： | SII1161 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
SiI
1161
PanelLink Receiver
Data Sheet
SiI
-DS-0096-D
22
Feature Information
HSYNC De-jitter Function
HSYNC de-jitter enables the
SiI
1161 to operate properly even when the HSYNC signal contains jitter. Pin 1 is
used to enable or disable this circuit. Tying this pin high enables the HSYNC de-jitter circuitry while tying it low
disables the circuitry. The HSYNC de-jitter circuitry operates normally with most VESA standard timings. In most
modes, HSYNC and VSYNC total times and front and back porch times are multiples of four pixel times. If the
timings are not a multiple of four, operation is not guaranteed and the HSYNC de-jitter circuitry should be turned
off. When HSYNC de-jitter is enabled, the circuitry will introduce anywhere from 1 to 4 CLK delays in the HSYNC
signal relative to the output data.
Clock Detect Function
The
SiI
1161
includes a power saving feature: power down with clock detect circuit. The
SiI
1161
will go into a low
power mode when there is no video clock coming from the transmitter. In this mode, the entire chip is powered
down except the clock detect circuitry. During this mode, digital I/O are set to a high impedance (tri-state) mode.
The SCDT pin is driven LOW. A weak internal pull-down device brings each output to ground. The device power
down and wake-up times are shown in Figure 11 and Figure 12.
OCK_INV Function
OCK_INV affects the phase of the clock output as indicated in Figure 18. The setting of OCK_INV is selected by
a strap pin when in
SiI
161B (Compatible) mode, and by a register bit when in
SiI
1161 (Programmable) mode.
OCK_INV does not change the timing for the internal data latching. As shown in the figure, the clock normally
passes through two inverters, each with delay T
INV
. However, when OCK_INV is set to 1, the output clock only
passes through a single inverter.
This timing is described in the Calculating Setup and Hold Times section.
Figure 18. Block Diagram for OCK_INV
Q
Q
SET
CLR
D
Data
Clock
OCK_INV
QE[0..23]
QO[0..23]
ODCK
相關PDF資料 |
PDF描述 |
|---|---|
| SiI1161CT100 | PanelLink Receiver |
| SiI1161CTU | PanelLink Receiver |
| SII1162 | PanelLink Transmitter |
| SII1169 | PanelLink Receiver |
| SII1171 | PanelLink Receiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SII1161CT100 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1161CTU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1162 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
| SII1162CSU | 制造商:Silicon Image Inc 功能描述: |
| SII1169 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。