參數(shù)資料
型號: Si9243EY
廠商: Vishay Intertechnology,Inc.
英文描述: Single-Ended Bus Transceiver(提供雙向串行通訊的單端總線收發(fā)器)
中文描述: 單端總線收發(fā)器(提供雙向串行通訊的單端總線收發(fā)器)
文件頁數(shù): 3/4頁
文件大?。?/td> 34K
代理商: SI9243EY
Si9243EY
S-49720—Rev. E, 27-Sep-96
3
Test Conditions
Unless Otherwise Specified
Unless Otherw se Spec f ed
Limits
E Suffix: –40 to 125 C
Parameter
Symbol
V
DD
= 4.5 to 5.5 V, V
B
= 7.25 to 35 V
Temp
a
Min
b
Typ
c
Max
b
Unit
Receiver
L and K Input Low Voltage
V
ILK
Full
0.4 V
BAT
0.33 V
BAT
L and K Input High Voltage
V
IHK
Full
0.7 V
BAT
0.6 V
BAT
L and K Input Hysteresis
d
V
HYS
Full
0.1 V
BAT
V
RXL and RXK
Output Low Voltage
V
OLR
V
ILK
, V
ILL
= 0.33 V
BAT
I
OLR
= 1 mA
Full
0.4
RXL and RXK High Voltage
V
OHR
TX = 4 V
V
IHK
, V
IHL
= 0.70 V
BAT
I
OHR
= –40 A
Full
4
L and K Input Currents
I
IHK
V
IHK
= V
B
Full
1.5
20
A
Supplies
Bat Supply Current
I
BAT
TX = 1.5 V, K, L Open
Full
2.7
5.0
mA
Logic Supply Current
I
DD
TX = 1.5 V, K, L Open
Full
1
3.0
Miscellaneous
Baud Rate
BR
R
L
= 510 , C
L
= 10 nF
Full
10.4
kBaud
TX Minimum Pulse Width
d, e
t
TX
Full
1
s
a.
b.
c.
d.
e.
Room = 25 C, Cold and Hot = as determined by the operating temperature suffix.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Guaranteed by design, not subject to production test.
Minimum pulse width to reset a fault condition.
Test Circuit
V
BAT
V
DD
GND
K
TX
Si9243EY
V
BAT
R
L
C
L
80%
80%
20%
20%
V
K
t
r
t
f
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