- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2109 > SI5375B-A-GL (Silicon Laboratories Inc)IC CLK GEN/JITTER ATTEN 80LBGA PDF資料下載
參數(shù)資料
| 型號： | SI5375B-A-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN/JITTER ATTEN 80LBGA |
| 標準包裝： | 240 |
| 系列： | DSPLL® |
| 類型： | 時鐘發(fā)生器，漂移衰減器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 808MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LBGA |
| 供應商設備封裝： | 80-BGA（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 336-2045 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Si5375
16
Rev. 1.0
5. Si5375 Application Examples and Suggestions
5.1. Schematic and PCB Layout
For a typical application schematic and PCB layout, see the Si537x-EVB Evaluation Board User's Guide, which
can be downloaded from www.silabs.com/timing.
In order to preserve the ultra low jitter of the Si5375 in applications where the four different DSPLL's are each
operating at different frequency, special care and attention must be paid to the PCB layout. The following is a list of
rules that should be observed:
1. The four VDD supplies should be isolated from one another with four ferrite beads. They should be
separately bypassed with capacitors that are located very close to the Si5375 device.
2. Use a solid and undisturbed ground plane for the Si5375 and all of the clock input and output return paths.
3. For applications that wish to logically connect the four RESET signals, do not tie them together underneath
the BGA package. Instead connect them outside of the BGA footprint.
4. As much as is possible, do not route clock input and output signals underneath the BGA package. The
clock output signals should go directly outwards from the BGA footprint.
5. Avoid placing the OSC_P and OSC_N signals on the same layer as the clock outputs. Add grounded guard
traces surrounding the OSC_P and OSC_N signals.
6. Where possible, place the CKOUT and CKIN signals on separate PCB layers with a ground layer between
them. The use of ground guard traces between all clock inputs and outputs is recommended.
For more information, see the Si537x-EVB Evaluation Board User's Guide and Appendix I of the Si53xx Reference
Manual, Rev 0.5 or higher.
5.2. Thermal Considerations
The Si5375 dissipates a significant amount of heat and it is important to take this into consideration when designing
the Si5375 operating environment. Among other issues, high die temperatures can result in increased jitter and
decreased long term reliability. It is therefore recommended that one or more of the following occur:
1. Use a heat sink: A heat sink example is Aavid part number 375324B00035G.
2. Use a VDD voltage of 1.8 V.
3. Limit the ambient temperature to significantly less that 85 °C.
4. Implement very good air flow.
5.3. SCL Leakage
When selecting pull up resistors for the two I2C signals, note that there is an internal pull down resistor of 18 k
from the SCL pin to ground. This comment does not apply to the SDA pin.
5.4. RSTL_x Pins
It is recommended that the four RSTL_x pins (RSTL_A, RSTL_B, RSTL_C and RSTL_D) be logically connected
together such that all four DSPLLs are either in or out of reset mode. When a DSPLL is in reset mode, its VCO will
not be locked to any signal and may drift across its operating range. If a drifting VCO has a frequency similar to that
of an operating VCO, there could be some crosstalk between the two VCOs. To avoid this from occurring during
device initialization, DSPLLsim loads each DSPLL with default Free Run frequency plans with VCO values apart
from one another. If the four RSTL_x pins are directly connected to one another, the connections should not be
made directly underneath the BGA package. Instead, the connections should be made outside the package
footprint.
相關PDF資料 |
PDF描述 |
|---|---|
| SI8241CB-B-IS1 | IC AUDIO DRIVER PWM 16-SOIC |
| SKY72300-21 | IC SYNTHESIZER 2.1GHZ 28-EPTSSOP |
| SKY72300-362 | IC SYNTHESIZER 2.1GHZ 24QFN |
| SKY72301-22 | IC SYNTHESIZER 1GHZ 28-EPTSSOP |
| SKY72310-362 | IC SYNTHESIZER 2.1GHZ 24QFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| Si5375-EVB | 功能描述:時鐘和定時器開發(fā)工具 QUAD DSPLL 4IN/4OUT CLOCK EVAL KIT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5376B-A-BL | 制造商:Silicon Laboratories Inc 功能描述:QUAD DSPLL JITTER ATTENUATING CLOCK, - Trays 制造商:Silicon Laboratories Inc 功能描述:IC CLK GEN/JITTER ATTEN 80PBGA |
| SI5376B-A-GL | 制造商:Silicon Laboratories Inc 功能描述:QUAD DSPLL JITTER ATTENUATING CLOCK, - Trays 制造商:Silicon Laboratories Inc 功能描述:IC CLK GEN/JITTER ATTEN 80PBGA 制造商:Silicon Laboratories Inc 功能描述:Phase Locked Loops - PLL QuadDSPLL 8 In/Outpt (2 kHz-808 MHz) |
| SI5380A-B-GM | 功能描述:IC CLOCK GEN TO 1.47456GHZ 64QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:LVCMOS，LVDS，LVPECL，晶體 輸出:CML，LVCMOS，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:5:12 差分 - 輸入:輸出:是/是 頻率 - 最大值:1.47GHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.47 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應商器件封裝:64-QFN（9x9） 標準包裝:260 |
| SI5380A-D-GM | 功能描述:BASE/BLANK PROTOTYPING DEVICE:UL 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):新產(chǎn)品 類型:* PLL:是 輸入:LVCMOS，LVDS，LVPECL，晶體 輸出:CML，LVCMOS，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:5:12 差分 - 輸入:輸出:是/是 頻率 - 最大值:1.47GHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.47 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應商器件封裝:64-QFN（9x9） 標準包裝:260 |
發(fā)布緊急采購，3分鐘左右您將得到回復。