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參數(shù)資料
| 型號： | SI5375B-A-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN/JITTER ATTEN 80LBGA |
| 標準包裝： | 240 |
| 系列： | DSPLL® |
| 類型： | 時鐘發(fā)生器，漂移衰減器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 808MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LBGA |
| 供應商設(shè)備封裝： | 80-BGA（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 336-2045 |
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Si5375
Rev. 1.0
15
4. Functional Description
Figure 5. Functional Block Diagram
The Si5375 is a highly integrated jitter-attenuating clock multiplier that integrates four fully independent DSPLLs
and provides ultra-low jitter generation with less than 410 fs RMS. The device accepts clock inputs ranging from
2 kHz to 710 MHz and generates independent, synchronous clock outputs ranging from 2 kHz to 808 MHz for each
DSPLL. Virtually any frequency translation (M/N) combination across its operating range is supported. The Si5375
supports a digitally programmable loop bandwidth that can range from 60 Hz to 8.4 kHz requiring no external loop
filter components. An external single-ended or differential reference clock or XO is required for the device to enable
ultra-low jitter generation and jitter attenuation. The Si5375 uses this external reference clock as both a jitter and
holdover reference. The reference clock can be either single-ended or differential and should be connected to the
OSC_P pin (and the OSC_N pin for differential signaling). Because there is very little jitter attenuation from the
OSC_P and OSC_N pins to the output clocks, a low-jitter reference clock is strongly recommended. The stability
during holdover is determined by the stability of the reference clock. For more details, see the description of
RATE_REG (register 2 on page 12) and the Any-Frequency Precision Clocks Family Reference Manual, which can
be downloaded from http://www.silabs.com/timing. The reference oscillator can be internally routed into CKIN2_q,
so free-running clock generation is supported for each DSPLL offering simultaneous synchronous and
asynchronous operation. Configuration and control of the Si5375 is primarily handled through the I2C interface.
The device monitors each input clock for Loss-of-Signal (LOS) and provides a LOS alarm when missing pulses on
any of the input clocks are detected. The device monitors the lock status of each DSPLL and provides a Loss-of-
Lock (LOL) alarm when the DSPLL is unlocked. The lock detect algorithm continuously monitors the phase of the
selected input clock in relation to the phase of the feedback clock. The Si5375 provides a VCO freeze capability
that allows the device to continue generation of a stable output clock when the input reference is lost.
The output drivers are configurable to support common signal formats, such as LVPECL, LVDS, CML, and CMOS
loads. If the CMOS signal format is selected, each differential output buffer generates two in-phase CMOS clocks
at the same frequency. For system-level debugging, a bypass mode drives the clock output directly from the
selected input clock, bypassing the internal DSPLL.
Silicon Laboratories offers a PC-based software utility, Si537xDSPLLsim that can be used to determine valid
frequency plans and loop bandwidth settings to simplify device setup. Si537xDSPLLsim provides the optimum
input, output, and feedback divider values for a given input frequency and clock multiplication ratio that minimizes
phase noise. This utility can be downloaded from http://www.silabs.com/timing. For further assistance, refer to the
Si53xx Any-Frequency Precision Clocks Family Reference Manual.
CKIN1P_B
÷ N31
DSPLL
B
CKIN1N_B
÷ N32
fOSC
÷ NC1_HS
Input
Monitor
f3
÷ N2
Status / Control
PLL Bypass
High PSRR
Voltage Regulator
VDD_q
GND
Synthesis Stage
CKIN1P_A
CKOUT1N_A
÷ N31
DSPLL
A
CKIN1N_A
÷ N32
CKOUT1P_A
Output Stage
fOSC
÷ NC1_HS
Input
Monitor
f3
÷ N2
PLL Bypass
Input Stage
CKIN1P_D
÷ N31
DSPLL
D
CKIN1N_D
÷ N32
fOSC
÷ NC1_HS
Input
Monitor
f3
÷ N2
PLL Bypass
CKIN1P_C
÷ N31
DSPLL
C
CKIN1N_C
÷ N32
fOSC
÷ NC1_HS
Input
Monitor
f3
÷ N2
PLL Bypass
RSTL_q
CS_q
SCL
SDA LOL_q IRQ_q
Low Jitter
XO or Clock
OSC_P/N
÷ NC1
PLL Bypass
CKOUT1N_B
÷ NC1
PLL Bypass
CKOUT1P_B
CKOUT1N_C
PLL Bypass
CKOUT1P_C
÷ NC1
CKOUT1N_D
÷ NC1
PLL Bypass
CKOUT1P_D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5375-EVB | 功能描述:時鐘和定時器開發(fā)工具 QUAD DSPLL 4IN/4OUT CLOCK EVAL KIT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5376B-A-BL | 制造商:Silicon Laboratories Inc 功能描述:QUAD DSPLL JITTER ATTENUATING CLOCK, - Trays 制造商:Silicon Laboratories Inc 功能描述:IC CLK GEN/JITTER ATTEN 80PBGA |
| SI5376B-A-GL | 制造商:Silicon Laboratories Inc 功能描述:QUAD DSPLL JITTER ATTENUATING CLOCK, - Trays 制造商:Silicon Laboratories Inc 功能描述:IC CLK GEN/JITTER ATTEN 80PBGA 制造商:Silicon Laboratories Inc 功能描述:Phase Locked Loops - PLL QuadDSPLL 8 In/Outpt (2 kHz-808 MHz) |
| SI5380A-B-GM | 功能描述:IC CLOCK GEN TO 1.47456GHZ 64QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:LVCMOS，LVDS，LVPECL，晶體 輸出:CML，LVCMOS，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:5:12 差分 - 輸入:輸出:是/是 頻率 - 最大值:1.47GHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.47 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應商器件封裝:64-QFN（9x9） 標準包裝:260 |
| SI5380A-D-GM | 功能描述:BASE/BLANK PROTOTYPING DEVICE:UL 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):新產(chǎn)品 類型:* PLL:是 輸入:LVCMOS，LVDS，LVPECL，晶體 輸出:CML，LVCMOS，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:5:12 差分 - 輸入:輸出:是/是 頻率 - 最大值:1.47GHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.47 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應商器件封裝:64-QFN（9x9） 標準包裝:260 |
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