The Si5374 has four identical register maps for each DSPLL. Each DSPLL has a unique I
參數(shù)資料
型號: SI5374B-A-GL
廠商: Silicon Laboratories Inc
文件頁數(shù): 13/69頁
文件大?。?/td> 0K
描述: IC CLK GEN/JITTER ATTEN 80LBGA
標(biāo)準(zhǔn)包裝: 240
系列: DSPLL®
類型: 時鐘發(fā)生器,漂移衰減器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 8:8
差分 - 輸入:輸出: 是/是
頻率 - 最大: 808MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LBGA
供應(yīng)商設(shè)備封裝: 80-BGA(10x10)
包裝: 托盤
其它名稱: 336-2046
Si5374
20
Rev. 1.1
6. Register Map
The Si5374 has four identical register maps for each DSPLL. Each DSPLL has a unique I2C address enabling
independent control and device configuration. The I2C address is 11010 [A1] [A0] for the entire device. Each
corresponding DSPLL [A1] [A0] address is fixed as below.
[A1] [A0]
DSPLLA:
0
DSPLLB:
0
1
DSPLLC:
1
0
DSPLLD:
1
Note:
The Si5374 register map is similar, but not identical, to the Si5324 device.
All register bits that are not defined in this map should always be written with the specific reset values. Writing to
these bits with values other than the specified reset values may result in undefined device behavior. Registers not
listed, such as Register 64, should never be written to.
Table 8. Si5374 Registers
Reg.
D7
D6
D5
D4
D3
D2
D1
D0
0
FREE_RU
N
CKOUT_
ALWAYS_ON
BYPASS_REG
1
CK_PRIOR2[1:0]
CK_PRIOR1[1:0]
2
BWSEL_REG[3:0]
RATE_REG [3:0]
3
CKSEL_REG[1:0]
DHOLD
SQ_ICAL
4
AUTOSEL_REG[1:0]
HIST_DEL[4:0]
5
ICMOS[1:0]
6
SFOUT2_REG[2:0}
SFOUT1_REG[2:0]
7
FOSREFSEL[2:0]
8
HLOG_2[1:0]
HLOG_1[1:0]
9
HIST_AVG[4:0]
10
DSBL2_ REG
DSBL1_ REG
11
PD_CK2
PD_CK1
19
FOS_EN
FOS_THR[1:0]
VALTIME[1:0]
LOCKT[2:0]
20
Write 0
LOL_PIN
IRQ_PIN
21
Write 0
CK1_ACT-
V_PIN
CKSEL_PIN
22
CK_ACTV_
POL
LOL_POL
INT_POL
23
LOS2_MSK
LOS1_MSK
LOSX_MSK
24
FOS2_MSK
FOS1_MSK
LOL_MSK
25
N1_HS[2:0]
31
NC1_LS[19:16]
32
NC1_LS[15:8]
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