Si5368
Rev. 1.0
9
Table 3. AC Specifications
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XARIN
RATE[1:0] = LM, MH,
ac coupled
—12
—
k
Input Voltage Swing
XAVPP
RATE[1:0] = LM, MH,
ac coupled
0.5
—
1.2
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
XA/XBVPP
RATE[1:0] = LM, MH
0.5
—
2.4
VPP
CKINn Input Pins
Input Frequency
CKNF
Input frequency and clock
multiplication ratio deter-
mined by programming
device PLL dividers. Con-
sult Silicon Laboratories
configuration software
DSPLLsim or Any-Fre-
quency Precision Clock
Family Reference Manual
at www.silabs.com/timing
(click on Documentation)
to determine PLL divider
settings for a given input
frequency/clock multiplica-
tion ratio combination
0.002
—
710
MHz
Input Clock Frequency
(CKIN3, CKIN4 used
as FSYNC inputs)
CKF
0.002
—
0.512
MHz
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
40
—
60
%
2—
—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.