3-Level Input Pins4 Input Voltage Low VILL
參數(shù)資料
型號: SI5368A-C-GQ
廠商: Silicon Laboratories Inc
文件頁數(shù): 78/92頁
文件大?。?/td> 0K
描述: IC CLK MULTIPLIER ATTEN 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSPLL®
類型: 時(shí)鐘放大器,振動(dòng)衰減器
PLL:
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.42GHz
除法器/乘法器: 無/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
Si5368
8
Rev. 1.0
3-Level Input Pins4
Input Voltage Low
VILL
0.15 x VDD
V
Input Voltage Mid
VIMM
0.45 x
VDD
—0.55 x VDD
V
Input Voltage High
VIHH
0.85 x
VDD
——
V
Input Low Current
IILL
See Note 4
–20
A
Input Mid Current
IIMM
See Note 4
–2
+2
A
Input High Current
IIHH
See Note 4
20
A
LVCMOS Output Pins
Output Voltage Low
VOL
IO = 2 mA
VDD =1.71V
——
0.4
V
Output Voltage Low
IO = 2 mA
VDD =2.97V
——
0.4
V
Output Voltage High
VOH
IO = –2 mA
VDD =1.71V
VDD –0.4
V
Output Voltage High
IO = –2 mA
VDD =2.97V
VDD –0.4
V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD
≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
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