參數(shù)資料
型號: SI5368A-C-GQ
廠商: Silicon Laboratories Inc
文件頁數(shù): 25/92頁
文件大小: 0K
描述: IC CLK MULTIPLIER ATTEN 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSPLL®
類型: 時鐘放大器,振動衰減器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.42GHz
除法器/乘法器: 無/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
Si5368
Rev. 1.0
31
Reset value = 0010 1100
Register 6.
Bit
D7D6D5D4D3D2D1
D0
Name
SFOUT4_REG [2:0]
SFOUT3_REG [2:0]
Type
RR
R/W
Bit
Name
Function
7:6
Reserved
5:3
SFOUT4_REG [2:0]
SFOUT4_REG [2:0].
Controls output signal format and disable for CKOUT4 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or
CML; however, there are restrictions in the allowed output format pin settings so
that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs,
the fifth output must be disabled. When there are five enabled outputs, there can
be no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported.)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
SFOUT3_REG [2:0]
SFOUT3_REG [2:0].
Controls output signal format and disable for CKOUT3 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or
CML; however, there are restrictions in the allowed output format pin settings so
that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs,
the fifth output must be disabled. When there are five enabled outputs, there can
be no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported.)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
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