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參數(shù)資料
| 型號： | SI5364-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 19/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SONET/SDH PORT 99LFBGA |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | DSPLL® |
| 類型： | 時鐘發(fā)生器，扇出緩沖器（分配） |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 675MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應(yīng)商設(shè)備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5364
26
Rev. 2.5
D10
LOS_F
O
LVTTL
Loss-of-Signal (LOS) Alarm for REF/CLKIN_F.
See LOS_A.
A5
FOS_A
O
LVTTL
Frequency Offset (FOS) Alarm for CLKIN_A.
Active high output indicates that the frequency offset
between CLKIN_A and REF/CLKIN_F exceeds the
selectable frequency offset threshold. The offset
threshold is selected by the SMC/S3N input. This
output can be disabled with the DSBLFOS control
input.
A6
FOS_B
O
LVTTL
Frequency Offset (FOS) Alarm for CLKIN_B.
See FOS_A.
B9
SMC/S3N
I*
LVTTL
SONET Minimum Clock/Stratum3-3E.
Sets the frequency offset threshold used to trigger
the FOS_A and FOS_B alarm outputs.
0 = 9.2–16.6 ppm for Stratum 3/3E operation.
1 = 40–72 ppm for SONET Minimum Clock opera-
tion.
B5
DSBLFOS
I*
LVTTL
Disable FOS.
When high, all frequency offset comparison and error
generation functionality is disabled. When Disable
FOS is active, the FOS_A and FOS_B outputs are
low, and automatic switching is based only on loss-
of-signal (LOS) status.
A4
B4
MANCNTRL[0]
MANCNTRL[1]
I*
LVTTL
Manual Switching Control.
Selects the input clock used by the DSPLL to gener-
ate the SONET/SDH clock outputs. Selection of digi-
tal hold mode locks the current state of the DSPLL
and forces the DSPLL to continue generation of the
output clocks with no additional phase or frequency
information from the input clocks. The MANCNTRL
inputs are internally deglitched to prevent inadvertent
clock switching during changes in the MANCNTRL
state.
The MANCNTRL[1:0] inputs are decoded as follows:
00 = Manual selection of REF/CLKIN_F.
01 = Manual selection of CLKIN_B.
10 = Manual selection of CLKIN_A.
11 = Digital hold mode.
The MANCNTRL inputs are ignored when the AUTO-
SEL input is high.
Table 10. Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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| Si5364-H-GLR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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| SI5365-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
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