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參數(shù)資料
| 型號： | SI5364-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 14/38頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SONET/SDH PORT 99LFBGA |
| 標準包裝： | 168 |
| 系列： | DSPLL® |
| 類型： | 時鐘發(fā)生器，扇出緩沖器（分配） |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 675MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應商設(shè)備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5364
Rev. 2.5
21
and are also used for connection of the external
compensation circuit.
The compensation circuit for the internal voltage
regulator consists of a resistor and a capacitor in series
between the VDD25 node and ground. In practice, if a
capacitor is selected with an appropriate equivalent
series resistance (ESR), the discrete series resistor can
be eliminated. The target RC time constant for this
combination is 15 to 50 s. The capacitor used in the
Si5364 evaluation board is a 33 F tantalum capacitor
with an ESR of 0.8
Ω. This gives an RC time constant of
26.4 s and no discrete resistor is required. (See
The Venkel part number,
TA6R3TCR336KBR, is an example of a capacitor that
meets these specifications.
To get optimal performance from the Si5364 device, the
power supply noise spectrum must comply with the plot
in Figure 13. This plot shows the power supply noise
tolerance mask for the Si5364. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5364, consider the following:
Use an isolated, local plane to connect the VDD25
pins. Avoid running signal traces over or below this
plane without a ground plane in between.
Route all I/O traces between ground planes as much
as possible
Maintain an input clock amplitude in the 200 mVPP to
500 mVPP differential range.
Excessive high-frequency harmonics of the input clock
should be minimized. The use of filters on the input
clock signal can be used to remove high-frequency
harmonics.
Figure 13. Power Supply Noise Tolerance Mask
f
Vn (μV/√Hz)
230
4.5
10 kHz
500 kHz
100 Mhz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5364-H-GLR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5365 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER |
| Si5365/66-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5365/Si5366 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| Si5365-B-GQ | 功能描述:時鐘合成器/抖動清除器 PIN-PROGRAMMABLE CLK MULTIPLIER 5 OUTS RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5365-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
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