參數(shù)資料
型號: SI5324C-C-GMR
廠商: Silicon Laboratories Inc
文件頁數(shù): 19/72頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-346MHZ 36VQFN
標準包裝: 250
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應商設備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5324
26
Rev. 1.1
5. Register Descriptions
Reset value = 0001 0100
Register 0.
Bit
D7
D6
D5
D4D3D2
D1
D0
Name
FREE_RUN
CKOUT_
ALWAYS_ON
BYPASS_
REG
Type
R
R/W
R
R/W
R
Bit
Name
Function
7
Reserved
Reserved.
6FREE_RUN
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB
reference.
0: Disable
1: Enable
5CKOUT_
ALWAYS_ON
CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 11 on page 25.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output.
Notes:
1. The frequency may be significantly off until the part is calibrated.
2. Must be 1 to control output to output skew.
4:2
Reserved
Reserved.
1
BYPASS_
REG
Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device is in digital
hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.
0
Reserved
Reserved.
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